{"id":81383,"date":"2024-10-17T18:54:11","date_gmt":"2024-10-17T18:54:11","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-iec-61691-5-2004\/"},"modified":"2024-10-24T19:46:34","modified_gmt":"2024-10-24T19:46:34","slug":"ieee-iec-61691-5-2004","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-iec-61691-5-2004\/","title":{"rendered":"IEEE IEC 61691 5 2004"},"content":{"rendered":"

New IEEE Standard – Active. IEC 61691-5: 2004 Dual-logo document. Will replace IEEE Std 1076.4-2000. The VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Speci cation is de ned in this standard.This modeling speci cation de nes a methodology which promotes the development of highly accurate, ef cient simulation models for ASIC (Application-Speci c Integrated Circuit)components in VHDL.<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
4<\/td>\nCONTENTS <\/td>\n<\/tr>\n
6<\/td>\nForeword <\/td>\n<\/tr>\n
10<\/td>\nIEEE Introduction <\/td>\n<\/tr>\n
12<\/td>\n1. Overview
1.1 Scope
1.2 Purpose
1.3 Intent of this standard
1.4 Structure and terminology of this standard <\/td>\n<\/tr>\n
13<\/td>\n1.5 Syntactic description <\/td>\n<\/tr>\n
14<\/td>\n1.6 Semantic description
1.7 Front matter, examples, figures, notes, and annexes
2. References <\/td>\n<\/tr>\n
15<\/td>\n3. Basic elements of the VITAL ASIC modeling specification
3.1 VITAL modeling levels and compliance <\/td>\n<\/tr>\n
16<\/td>\n3.2 VITAL standard packages
3.3 VITAL specification for timing data insertion <\/td>\n<\/tr>\n
18<\/td>\n4. The Level 0 specification
4.1 The VITAL_Level0 attribute
4.2 General usage rules <\/td>\n<\/tr>\n
19<\/td>\n4.3 The Level 0 entity interface <\/td>\n<\/tr>\n
28<\/td>\n4.4 The Level 0 architecture body <\/td>\n<\/tr>\n
30<\/td>\n5. Backannotation
5.1 Backannotation methods <\/td>\n<\/tr>\n
31<\/td>\n5.2 The VITAL SDF map <\/td>\n<\/tr>\n
46<\/td>\n6. The Level 1 specification
6.1 The VITAL_Level1 attribute
6.2 The Level 1 architecture body <\/td>\n<\/tr>\n
47<\/td>\n6.3 The Level 1 architecture declarative part
6.4 The Level 1 architecture statement part <\/td>\n<\/tr>\n
57<\/td>\n7. Predefined primitives and tables
7.1 VITAL logic primitives <\/td>\n<\/tr>\n
59<\/td>\n7.2 VitalResolve
7.3 VITAL table primitives <\/td>\n<\/tr>\n
65<\/td>\n8. Timing constraints
8.1 Timing check procedures <\/td>\n<\/tr>\n
70<\/td>\n8.2 Modeling negative timing constraints <\/td>\n<\/tr>\n
81<\/td>\n9. Delay selection
9.1 VITAL delay types and subtypes <\/td>\n<\/tr>\n
82<\/td>\n9.2 Transition dependent delay selection
9.3 Glitch handling <\/td>\n<\/tr>\n
83<\/td>\n9.4 Path delay procedures <\/td>\n<\/tr>\n
85<\/td>\n9.5 Delay selection in VITAL primitives <\/td>\n<\/tr>\n
86<\/td>\n9.6 VitalExtendToFillDelay <\/td>\n<\/tr>\n
87<\/td>\n10. The Level 1 Memory specification
10.1 The VITAL Level 1 Memory attribute
10.2 The VITAL Level 1 Memory architecture body <\/td>\n<\/tr>\n
88<\/td>\n10.3 The VITAL Level 1 Memory architecture declarative part
10.4 The VITAL Level 1 Memory architecture statement part <\/td>\n<\/tr>\n
98<\/td>\n11. VITAL Memory function specification
11.1 VITAL memory construction <\/td>\n<\/tr>\n
101<\/td>\n11.2 VITAL memory table specification <\/td>\n<\/tr>\n
110<\/td>\n11.3 VitalDeclareMemory <\/td>\n<\/tr>\n
112<\/td>\n11.4 VitalMemoryTable <\/td>\n<\/tr>\n
114<\/td>\n11.5 VitalMemoryCrossPorts <\/td>\n<\/tr>\n
116<\/td>\n11.6 VitalMemoryViolation <\/td>\n<\/tr>\n
119<\/td>\n12. VITAL memory timing specification
12.1 VITAL memory timing types <\/td>\n<\/tr>\n
120<\/td>\n12.2 Memory Output Retain timing behavior <\/td>\n<\/tr>\n
121<\/td>\n12.3 VITAL Memory output retain timing specification
12.4 Transition dependent delay selection <\/td>\n<\/tr>\n
122<\/td>\n12.5 VITAL memory path delay procedures <\/td>\n<\/tr>\n
127<\/td>\n12.6 VITAL memory timing check procedures <\/td>\n<\/tr>\n
132<\/td>\n13. The VITAL standard packages
13.1 VITAL_Timing package declaration <\/td>\n<\/tr>\n
147<\/td>\n13.2 VITAL_Timing package body <\/td>\n<\/tr>\n
174<\/td>\n13.3 VITAL_Primitives package declaration <\/td>\n<\/tr>\n
243<\/td>\n13.4 VITAL_Primitives package body <\/td>\n<\/tr>\n
313<\/td>\n13.5 VITAL_Memory package declaration <\/td>\n<\/tr>\n
334<\/td>\n13.6 VITAL_Memory package body <\/td>\n<\/tr>\n
423<\/td>\nAnnex A (informative) Syntax summary <\/td>\n<\/tr>\n
429<\/td>\nAnnex B (informative) Glossary <\/td>\n<\/tr>\n
431<\/td>\nAnnex C (informative) Bibliography <\/td>\n<\/tr>\n
432<\/td>\nAnnex D (informative) List of Participants <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEC 61691-5 Ed.1 (IEEE Std 1076.4(TM)-2000): Behavioural Languages – Part 5: Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2004<\/td>\n436<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":81384,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-81383","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/81383","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/81384"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=81383"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=81383"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=81383"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}