{"id":236767,"date":"2024-10-19T15:27:28","date_gmt":"2024-10-19T15:27:28","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-en-60679-12017\/"},"modified":"2024-10-25T10:05:03","modified_gmt":"2024-10-25T10:05:03","slug":"bs-en-60679-12017","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-en-60679-12017\/","title":{"rendered":"BS EN 60679-1:2017"},"content":{"rendered":"
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
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2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
7<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
9<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | 1 Scope 2 Normative references <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | 3 Terms, definitions and general information 3.1 General 3.2 Terms and definitions <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | Figures Figure 1 \u2013 Basic configurations of SAW resonators <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | Figure 2 \u2013 Example of the use of frequency offset <\/td>\n<\/tr>\n | ||||||
21<\/td>\n | Figure 3 \u2013 Linearity of frequency modulation deviation <\/td>\n<\/tr>\n | ||||||
23<\/td>\n | Figure 4 \u2013 Characteristics of an output waveform <\/td>\n<\/tr>\n | ||||||
24<\/td>\n | Figure 5 \u2013 Definition of start-up time Figure 6 \u2013 Clock signal with period jitter <\/td>\n<\/tr>\n | ||||||
25<\/td>\n | Figure 7 \u2013 Phase jitter measures Figure 8 \u2013 Gaussian distribution of jitter Figure 9 \u2013 Jitter amplitude and period of jitter frequency <\/td>\n<\/tr>\n | ||||||
26<\/td>\n | 3.3 Preferred values for ratings and characteristics 3.3.1 General Figure 10 \u2013 Jitter tolerance according to ITU-T G.825, ATIS-0900101,Telcordia GR-253 and ETSI EN 300 462 <\/td>\n<\/tr>\n | ||||||
27<\/td>\n | 3.3.2 Climatic category (40\/85\/56) 3.3.3 Bump severity 3.3.4 Vibration severity 3.3.5 Shock severity 3.3.6 Leak rate <\/td>\n<\/tr>\n | ||||||
28<\/td>\n | 3.4 Marking 3.4.1 General 3.4.2 Packaging 4 Quality assessment procedures 4.1 General 4.2 Primary stage of manufacture 4.3 Structurally similar components 4.4 Subcontracting <\/td>\n<\/tr>\n | ||||||
29<\/td>\n | 4.5 Incorporated components 4.6 Manufacturer\u2019s approval 4.7 Approval procedures 4.7.1 General 4.7.2 Capability approval 4.7.3 Qualification approval <\/td>\n<\/tr>\n | ||||||
30<\/td>\n | 4.8 Procedures for capability approval 4.8.1 General 4.8.2 Eligibility for capability approval 4.8.3 Application for capability approval 4.8.4 Granting of capability approval 4.8.5 Capability manual 4.9 Procedures for qualification approval 4.9.1 General 4.9.2 Eligibility for qualification approval 4.9.3 Application for qualification approval 4.9.4 Granting of qualification approval <\/td>\n<\/tr>\n | ||||||
31<\/td>\n | 4.9.5 Quality conformance inspection 4.10 Test procedures 4.11 Screening requirements 4.12 Rework and repair work 4.12.1 Rework 4.12.2 Repair work 4.13 Certified test records 4.14 Validity of release 4.15 Release for delivery <\/td>\n<\/tr>\n | ||||||
32<\/td>\n | 4.16 Unchecked parameters <\/td>\n<\/tr>\n | ||||||
33<\/td>\n | Annex A (normative) Load circuit for logic drive A.1 TTL and Schottky Figure A.1 \u2013 Circuit for TTL <\/td>\n<\/tr>\n | ||||||
34<\/td>\n | Figure A.2 \u2013 Circuit for Schottky logic <\/td>\n<\/tr>\n | ||||||
35<\/td>\n | A.2 CMOS A.3 ECL Figure A.3 \u2013 Circuit for PECL Tables Table A.1 \u2013 Values to be used when calculating R1 and R2 <\/td>\n<\/tr>\n | ||||||
36<\/td>\n | A.4 LVDS Figure A.4 \u2013 Circuit for LVDS Table A.2 \u2013 Operating condition Table A.3 \u2013 DC Electrical characteristics output load = 50 \u2126 to Vcc-2V <\/td>\n<\/tr>\n | ||||||
37<\/td>\n | Annex B (normative) Latch-up test B.1 Definition B.1.1 Latch-up B.1.2 Test procedure B.2 Test method <\/td>\n<\/tr>\n | ||||||
38<\/td>\n | Annex C (normative) Electrostatic discharge sensitivity classification C.1 Definition C.1.1 Electrostatic discharge (ESD) C.1.2 Test procedure C.2 Test methods C.2.1 General C.2.2 Leaded oscillator C.2.3 SMD oscillator C.2.4 The impact of ESD on Oscillator in steady-state <\/td>\n<\/tr>\n | ||||||
39<\/td>\n | Annex D (normative) Digital interfaced crystal oscillator\u2019s function Table D.1 \u2013 Function of the digital interface <\/td>\n<\/tr>\n | ||||||
40<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Piezoelectric, dielectric and electrostatic oscillators of assessed quality – Generic specification<\/b><\/p>\n |