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BS EN IEC 61158-4-24:2023 – TC

BS EN IEC 61158-4-24:2023 – TC

$280.87

Tracked Changes. Industrial communication networks. Fieldbus specifications – Data-link layer protocol specification. Type 24 elements

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BSI 2023 508
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PDF Catalog

PDF Pages PDF Title
1 30476456_New
185 30476456_New
369 A-30473951
370 undefined
373 Annex ZA (normative)Normative references to international publicationswith their corresponding European publications
374 CONTENTS
379 FOREWORD
381 INTRODUCTION
382 1 Scope
1.1 General
1.2 Specifications
1.3 Procedures
383 1.4 Applicability
1.5 Conformance
2 Normative references
384 3 Terms, definitions, symbols, abbreviated terms and conventions
3.1 Reference model terms and definitions
385 3.2 Service convention terms and definitions
3.3 Common terms and definitions
388 3.4 Symbols and abbreviations
3.5 Additional Type 24 symbols and abbreviations
3.6 Common conventions
389 3.7 Additional Type 24 conventions
3.7.1 Primitive conventions
3.7.2 State machine conventions
390 4 Overview of DL-protocol
4.1 Characteristic feature of the DL-protocol
Tables
Table 1 ā€“ State transition descriptions
Table 2 ā€“ Description of state machine elements
Table 3 ā€“ Conventions used in state machines
391 4.2 DL layer component
Table 4 ā€“ Characteristic features of the fieldbus data-link protocol
392 4.2.1 Cyclic transmission control (CTC)
4.2.2 Send receive control (SRC)
4.2.3 DL-management
4.3 Timing sequence
4.3.1 Overview
4.3.2 Cyclic transmission mode
Figures
Figure 1 ā€“ Data-link layer component
393 Figure 2 ā€“ Timing chart of fixed-width time slot type cyclic communication
395 Figure 3 ā€“ Timing chart of configurable time slot type cyclic communication
397 Figure 4 ā€“ Schematic diagram of cyclic event occurrence
400 Figure 5 ā€“ Timing relationship between cyclic transmission and data processing
Figure 6 ā€“ Timing chart of no time slot type cyclic communication (Master send common address)
401 Figure 7 ā€“ Timing chart for multiple transmission cycle setting
402 Figure 8 ā€“ Timing chart for multiple transmission cycle setting igure title
403 Figure 9 ā€“ Schematic diagram for connection
404 Figure 10 ā€“ Schematic diagram of INPUT data response timing at the same interval
405 Figure 11 ā€“ Schematic diagram of INPUT data response timing at the same time
406 4.3.3 Acyclic transmission mode
4.4 Service assumed from the PhL
4.4.1 General requirement
4.4.2 DL_Symbols
Figure 12 ā€“ Timing chart example of acyclic communication
407 4.4.3 Assumed primitives of the PhS
4.5 Local parameters, variables, counters, timers
4.5.1 Overview
4.5.2 Variables, parameters, counters and timers to support DLE function
408 Table 5 ā€“ List of the values of the variable Cyc_sel
409 Table 6 ā€“ List of the values of the variable Tunit
410 Table 7 ā€“ List of the values of the variable PDUType
Table 8 ā€“ List of the values of the variable SlotType
412 5 DLPDU structure
5.1 Overview
5.1.1 Transfer syntax for bit sequences
Table 9 ā€“ Transfer syntax for bit sequences
413 5.1.2 Data type encodings
5.1.3 Frame format
5.2 Basic format DLPDU structure
5.2.1 General
Table 10 ā€“ Bit order
414 Figure 13 ā€“ Basic format DLPDU structure
Table 11 ā€“ Destination and source address format
Table 12 ā€“ Station address
415 Table 13 ā€“ Extended address
Table 14 ā€“ Message control field format (Information transfer format)
416 Table 15 ā€“ Message control field format (Supervisory format)
Table 16 ā€“ The list of Supervisory function bits
Table 17 ā€“ Frame type and data length format
417 5.2.2 Synchronous frame
Table 18 ā€“ The list of Frame type
Table 19 ā€“ Data format of the Synchronous frame
418 5.2.3 Output data or Input data frame
5.2.4 Delay measurement start frame
Table 20 ā€“ The field list of the Synchronous frame
Table 21 ā€“ Data format of the Output data or the Input data frame
Table 22 ā€“ The field list of the Output data or the Input data frame
419 5.2.5 Delay measurement frame
5.2.6 Message token frame
Table 23 ā€“ Data format of Delay measurement start frame
Table 24 ā€“ The field list of Delay measurement start frame
Table 25 ā€“ Data format of Delay measurement frame
Table 26 ā€“ The field list of Delay measurement frame
420 5.2.7 Status frame
Table 27 ā€“ Data format of Status frame
Table 28 ā€“ The field list of Status frame
Table 29 ā€“ The list of the DLE status
421 5.2.8 Cycle Information frame
Table 30 ā€“ The list of Repeater status
Table 31 ā€“ Data format of Delay measurement frame
422 5.2.9 Message frame
Table 32 ā€“ The field list of Cycle Information frame
Table 33 ā€“ Data format of Message frame
Table 34 ā€“ The field list of Message frame
423 5.3 Short format DLPDU structure
5.3.1 General
Figure 14 ā€“ Short format DLPDU structure
Table 35 ā€“ Range of Station address field
424 Table 36 ā€“ Control field format (I/O data exchange format)
Table 37 ā€“ Control field format (Message format)
Table 38 ā€“ The field list of Message format
425 5.3.2 Synchronous frame
5.3.3 Output data or Input data frame
Table 39 ā€“ Data format of the Synchronous frame
Table 40 ā€“ The field list of the Synchronous frame
Table 41 ā€“ Data format of the Output data frame
426 5.3.4 Message frame
5.4 Short format II DLPDU structure
5.4.1 General
Figure 15 ā€“ Short format II DLPDU structure
Table 42 ā€“ The field list of the Output data frame
Table 43 ā€“ Data format of the Input data frame
Table 44 ā€“ The field list of the Input data frame
427 Figure 16 ā€“ Acyclic transmission frame address field
Figure 17 ā€“ Cyclic transmission frame address
Table 45 ā€“ Range of Station address field
428 5.4.2 Asynchronous frame
Figure 18 ā€“ Asynchronous frame
Table 46 ā€“ Cycle scale counter field format
Table 47 ā€“ The list of frame type
429 5.4.3 Synchronous frame
5.4.4 Output data or Input data frame
Figure 19 ā€“ Synchronous frame (to be used by C1)
Figure 20 ā€“ Synchronous frame (to be used by C2 or slave)
Table 48 ā€“ Data format of the Output data frame
Table 49 ā€“ The field list of the Output data frame
Table 50 ā€“ Data format of the Input data frame
430 6 DLE element procedure
6.1 Overview
6.2 Cyclic transmission control sublayer
6.2.1 General
6.2.2 DLS-user interface
Table 51 ā€“ The field list of the Input data frame
Table 52 ā€“ Primitives and parameters for the DLS-user interface issued by the DLSā€‘user
431 6.2.3 Protocol machines in CTC
Table 53 ā€“ Primitives and parameters for the DLS-user interface issued by the CTC
432 Figure 21 ā€“ The state diagram of the C1 master for fixed-width time slot
433 Table 54 ā€“ The state table of the C1 master for fixed-width time slot
439 Figure 22 ā€“ The state diagram of the C2 master for fixed-width time slot
Table 55 ā€“ The state table of the C2 master for fixed-width time slot
443 Figure 23 ā€“ The state diagram of the slave for fixed-width time slot
Table 56 ā€“ The state table of the slave for fixed-width time slot
445 Figure 24 ā€“ The state diagram of the C1 master for configurable time slot
446 Table 57 ā€“ The state table of the C1 master for configurable time slot
454 Figure 25 ā€“ The state diagram of the C2 master for configurable time slot
Table 58 ā€“ The state table of the C2 master for configurable time slot
457 Figure 26 ā€“ The state diagram of slave for configurable time slot
458 Table 59 ā€“ The state table of slave for configurable time slot
459 Table 60 ā€“ The list of functions used by cyclic transmission machine
461 Figure 27 ā€“ The state diagram of the C1 master for no time slot type
462 Figure 28 ā€“ The state diagram of the C2 master for no time slot type
Table 61 ā€“ The state table of the C1 master for no time slot type
463 Table 62 ā€“ The state table of the C2 master for no time slot type
464 Figure 29 ā€“ The state diagram of the Slave for no time slot type
Table 63 ā€“ The state table of the Slave for no time slot type
465 Figure 30 ā€“ The state diagram of message initiator for basic format
466 Table 64 ā€“ The state table of message initiator for basic format
469 Figure 31 ā€“ The state diagram of message responder for basic format
470 Table 65 ā€“ The state table of message responder for basic format
473 Figure 32 ā€“ The state diagram of message initiator for short format
474 Table 66 ā€“ The state table of message initiator for short format
478 Figure 33 ā€“ The state diagram of message responder for short format
Table 67 ā€“ The state table of message responder for short format
482 Table 68 ā€“ List of functions used by the message segmentation machine
483 Figure 34 ā€“ The state diagram of the acyclic transmission protocol machine
484 6.2.4 CTC-DLM interface
Table 69 ā€“ The state table of the acyclic transmission protocol machine
Table 70 ā€“ The list of functions used acyclic transmission protocol machine
485 6.3 Send Receive Control
6.3.1 General
Table 71 ā€“ Primitives and parameters exchanged between CTC and DLM
Table 72 ā€“ Error event primitive and parameters
486 6.3.2 SRC-CTC interface
6.3.3 Detailed specification of SRC
Table 73 ā€“ primitives and parameters for SRC-CTC interface
Table 74 ā€“ Send frame primitive and parameters
Table 75 ā€“ Receive frame primitives and parameters
487 Figure 35 ā€“ Internal architecture of one-port SRC
Figure 36 ā€“ Internal architecture of multi-port SRC
Figure 37 ā€“ Internal architecture of serializer
489 Figure 38 ā€“ Internal architecture of deserializer
491 6.3.4 SRC-DLM interface
Table 76 ā€“ Primitives and parameters exchanged between SRC and DLM
492 7 DL-management layer (DLM)
7.1 Overview
7.2 Primitive definitions
7.2.1 Primitives exchanged between DLMS-user and DLM
Table 77 ā€“ Get value primitive and parameters
Table 78 ā€“ Error event primitive and parameters
493 7.2.2 Parameters used with DLM primitives
7.3 DLM protocol machine
7.3.1 C1 master
Table 79 ā€“ The list of primitives and parameters (DLMS-user source)
Table 80 ā€“ The list of primitives and parameters (DLM source)
494 Figure 39 ā€“ State diagram of the C1 master DLM
Table 81 ā€“ State table of the C1 Master DLM
498 7.3.2 Slave and C2 master
499 Figure 40 ā€“ State diagram of the Slave and the C2 master DLM
Table 82 ā€“ State table of the Slave and the C2 master DLM
502 7.4 Functions
Table 83 ā€“ The list of the functions used by DLM protocol machine
503 7.5 DLM protocol machine for no time slot type
7.5.1 C1 master
504 Figure 41 ā€“ State diagram of the C1 master DLM for no time slot type
Table 84 ā€“ State table of the C1 Master DLM for no time slot type
505 7.5.2 C2 master and Slave
Figure 42 ā€“ State diagram of the C2 master and slaves DLM for no time slot type
Table 85 ā€“ State table of the C2 master and slaves DLM for no time slot type
506 7.6 Functions for no time slot type
507 Bibliography

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BS EN IEC 61158-4-24:2023 - TC
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