{"id":233715,"date":"2024-10-19T15:14:24","date_gmt":"2024-10-19T15:14:24","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-en-62433-42016\/"},"modified":"2024-10-25T09:44:56","modified_gmt":"2024-10-25T09:44:56","slug":"bs-en-62433-42016","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-en-62433-42016\/","title":{"rendered":"BS EN 62433-4:2016"},"content":{"rendered":"
IEC 62433-4:2016 specifies a flow for deriving a macro-model to allow the simulation of the conducted immunity levels of an integrated circuit (IC). This model is commonly called Integrated Circuit Immunity Model – Conducted Immunity, ICIM-CI. It is intended to be used for predicting the levels of immunity to conducted RF disturbances applied on IC pins. In order to evaluate the immunity threshold of an electronic device, this macro-model will be inserted in an electrical circuit simulation tool. This macro-model can be used to model both analogue and digital ICs (input\/output, digital core and supply). This macro-model does not take into account the non-linear effects of the IC. The added value of ICIM-CI is that it could also be used for immunity prediction at board and system level through simulations. This part of IEC 62433 has two main parts: – the electrical description of ICIM-CI macro-model elements; – a universal data exchange format called CIML based on XML. This format allows ICIM-CI to be encoded in a more useable and generic form for immunity simulation.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
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6<\/td>\n | English CONTENTS <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | 1 Scope 2 Normative references <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | 3 Terms, definitions, abbreviations and conventions 3.1 Terms and definitions <\/td>\n<\/tr>\n | ||||||
15<\/td>\n | 3.2 Abbreviations 3.3 Conventions <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | 4 Philosophy 5 ICIM-CI model description 5.1 General <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | Figures Figure 1 \u2013 Example of ICIM-CI model structure <\/td>\n<\/tr>\n | ||||||
18<\/td>\n | 5.2 PDN description Figure 2 \u2013 Example of an ICIM-CI model of an electronic board <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | 5.3 IBC description <\/td>\n<\/tr>\n | ||||||
20<\/td>\n | 5.4 IB description Figure 3 \u2013 Example of an IBC network Figure 4 \u2013 ICIM-CI model representation with different blocks <\/td>\n<\/tr>\n | ||||||
21<\/td>\n | 6 CIML format 6.1 General <\/td>\n<\/tr>\n | ||||||
22<\/td>\n | 6.2 CIML structure Figure 5 \u2013 CIML inheritance hierarchy <\/td>\n<\/tr>\n | ||||||
23<\/td>\n | 6.3 Global keywords 6.4 Header section <\/td>\n<\/tr>\n | ||||||
24<\/td>\n | 6.5 Lead definitions Tables Table 1 \u2013 Attributes of Lead keyword in the Lead_definitions section Table 2 \u2013 Compatibility between the Mode and Type fields for correct CIML annotation <\/td>\n<\/tr>\n | ||||||
25<\/td>\n | 6.6 SPICE macro-models Table 3 \u2013 Subckt definition <\/td>\n<\/tr>\n | ||||||
26<\/td>\n | Figure 6 \u2013 Example of a netlist file defining a sub-circuit <\/td>\n<\/tr>\n | ||||||
27<\/td>\n | 6.7 Validity section 6.7.1 General 6.7.2 Attribute definitions Table 4 \u2013 Definition of the Validity section <\/td>\n<\/tr>\n | ||||||
29<\/td>\n | 6.8 PDN 6.8.1 General Table 5 \u2013 Definition of the Lead keyword for Pdn section <\/td>\n<\/tr>\n | ||||||
30<\/td>\n | 6.8.2 Attribute definitions <\/td>\n<\/tr>\n | ||||||
32<\/td>\n | Table 6 \u2013 Valid data formats and their default units in the Pdn section Table 7 \u2013 Valid file extensions in the Pdn section <\/td>\n<\/tr>\n | ||||||
33<\/td>\n | 6.8.3 PDN for a single-ended input or output Figure 7 \u2013 PDN electrical schematics Figure 8 \u2013 PDN represented as a one-port black-box <\/td>\n<\/tr>\n | ||||||
34<\/td>\n | Table 8 \u2013 Valid fields of the Lead keyword for single-ended PDN <\/td>\n<\/tr>\n | ||||||
36<\/td>\n | Figure 9 \u2013 PDN represented as S-parameters in Touchstone format <\/td>\n<\/tr>\n | ||||||
37<\/td>\n | Figure 10 \u2013 PDN represented as two-port S-parameters in Touchstone format <\/td>\n<\/tr>\n | ||||||
38<\/td>\n | Figure 11 \u2013 Example structure for defining the PDN using circuit elements Table 9 \u2013 Netlist definition <\/td>\n<\/tr>\n | ||||||
39<\/td>\n | Figure 12 \u2013 Example of a single-ended PDN Netlist main circuit definition Figure 13 \u2013 Example of a single-ended PDN Netlist with both sub-circuit and main circuit definitions <\/td>\n<\/tr>\n | ||||||
40<\/td>\n | 6.8.4 PDN for a differential input <\/td>\n<\/tr>\n | ||||||
41<\/td>\n | Figure 14 \u2013 Differential input schematic Figure 15 \u2013 PDN represented as a two-port black-box Figure 16 \u2013 PDN data format for differential input or output <\/td>\n<\/tr>\n | ||||||
42<\/td>\n | Table 10 \u2013 Valid fields of the Lead keyword for differential PDN <\/td>\n<\/tr>\n | ||||||
43<\/td>\n | 6.8.5 PDN multi-port description Figure 17 \u2013 Differential inputs of an operational amplifier example <\/td>\n<\/tr>\n | ||||||
44<\/td>\n | 6.9 IBC 6.9.1 General Figure 18 \u2013 ICIM-CI Model for a 74HC08 component <\/td>\n<\/tr>\n | ||||||
45<\/td>\n | 6.9.2 Attribute definitions Table 11 \u2013 Differences between the Pdn and Ibc section fields <\/td>\n<\/tr>\n | ||||||
46<\/td>\n | 6.10 IB 6.10.1 General Table 12 \u2013 Valid fields of the Lead keyword for IBC definition <\/td>\n<\/tr>\n | ||||||
47<\/td>\n | 6.10.2 Attribute definitions Table 13 \u2013 Definition of the Lead keyword in Ib section <\/td>\n<\/tr>\n | ||||||
48<\/td>\n | Table 14 \u2013 Max_power_level definition <\/td>\n<\/tr>\n | ||||||
49<\/td>\n | Table 15 \u2013 Voltage, Current and Power definition Table 16 \u2013 Test_criteria definition <\/td>\n<\/tr>\n | ||||||
52<\/td>\n | 6.10.3 Description Table 17 \u2013 Default values of Unit_voltage, Unit_current and Unit_power tags as a function of data format Table 18 \u2013 Valid file extensions in the Ib section <\/td>\n<\/tr>\n | ||||||
54<\/td>\n | 7 Extraction 7.1 General 7.2 Environmental extraction constraints Figure 19 \u2013 Example IB file obtained from DPI measurement <\/td>\n<\/tr>\n | ||||||
55<\/td>\n | 7.3 PDN extraction 7.3.1 General 7.3.2 S-\/Z-\/Y-parameter measurement 7.3.3 RFIP technique <\/td>\n<\/tr>\n | ||||||
56<\/td>\n | 7.4 IB extraction 7.4.1 General 7.4.2 Direct RF power injection test method Figure 20 \u2013 Test setup of the DPI immunity measurement method as specified in IEC\u00a062132-4 <\/td>\n<\/tr>\n | ||||||
57<\/td>\n | Figure 21 \u2013 Principle of single and multi-pin DPI <\/td>\n<\/tr>\n | ||||||
58<\/td>\n | 7.4.3 RF Injection probe test method Figure 22 \u2013 Electrical representation of the DPI test setup <\/td>\n<\/tr>\n | ||||||
59<\/td>\n | Figure 23 \u2013 Test setup of the RFIP measurement method derived from the DPI method <\/td>\n<\/tr>\n | ||||||
60<\/td>\n | 7.5 IBC 8 Validation of ICIM-CI hypotheses 8.1 General Table 19 \u2013 Example of IB table pass\/fail criteria <\/td>\n<\/tr>\n | ||||||
61<\/td>\n | 8.2 Linearity Figure 24 \u2013 Example setup used for illustrating ICIM-CI hypotheses <\/td>\n<\/tr>\n | ||||||
62<\/td>\n | 8.3 Immunity criteria versus transmitted power Figure 25 \u2013 Example of linearity assumption validation <\/td>\n<\/tr>\n | ||||||
63<\/td>\n | 9 Model usage Figure 26 \u2013 Example of transmitted power criterion validation Figure 27 \u2013 Use of the ICIM-CI macro-model for simulation <\/td>\n<\/tr>\n | ||||||
65<\/td>\n | Annexes Annex A (normative) Preliminary definitions for XML representation A.1 XML basics A.1.1 XML declaration A.1.2 Basic elements A.1.3 Root element <\/td>\n<\/tr>\n | ||||||
66<\/td>\n | A.1.4 Comments A.1.5 Line terminations A.1.6 Element hierarchy A.1.7 Element attributes A.2 Keyword requirements A.2.1 General <\/td>\n<\/tr>\n | ||||||
67<\/td>\n | A.2.2 Keyword characters A.2.3 Keyword syntax A.2.4 File structure <\/td>\n<\/tr>\n | ||||||
68<\/td>\n | Figure A.1 \u2013 Multiple XML (CIML) files Figure A.2 \u2013 XML files with data files (*.dat) <\/td>\n<\/tr>\n | ||||||
69<\/td>\n | A.2.5 Values Figure A.3 \u2013 XML files with additional files <\/td>\n<\/tr>\n | ||||||
70<\/td>\n | Table A.1 \u2013 Valid logarithmic units <\/td>\n<\/tr>\n | ||||||
72<\/td>\n | Annex B (informative) ICIM-CI example with disturbance load Figure B.1 \u2013 ICIM-CI description applied to an oscillator stage for extracting IB <\/td>\n<\/tr>\n | ||||||
73<\/td>\n | Annex\u00a0C (informative) Conversions between parameter types C.1 General C.2 Single-ended input or output Figure C.1 \u2013 Single-ended DI <\/td>\n<\/tr>\n | ||||||
74<\/td>\n | C.3 Differential input or output Figure C.2 \u2013 Differential DI Figure C.3 \u2013 Two-port representation of a differential DI Table C.1 \u2013 Single-ended parameter conversion <\/td>\n<\/tr>\n | ||||||
75<\/td>\n | Table C.2 \u2013 Differential parameter conversion <\/td>\n<\/tr>\n | ||||||
76<\/td>\n | Figure\u00a0C.4 \u2013 Simulation of common-mode injection on a differential DI based on DPI Figure C.5 \u2013 Equivalent common-mode input impedance of a differential DI Figure C.6 \u2013 Determination of transmitted power for a differential DI <\/td>\n<\/tr>\n | ||||||
77<\/td>\n | Table C.3 \u2013 Power calculation <\/td>\n<\/tr>\n | ||||||
78<\/td>\n | Annex D (informative) Example of ICIM-CI macro-model in CIML format Figure D.1 \u2013 Test setup on an example LIN transceiver <\/td>\n<\/tr>\n | ||||||
80<\/td>\n | Figure D.2 \u2013 PDN data in touchstone format (s2p), data measured using VNA <\/td>\n<\/tr>\n | ||||||
81<\/td>\n | Figure D.3 \u2013 PDN data of leads 6 (LIN) and 7 (VCC) Figure D.4 \u2013 IB data in ASCII format (.txt), data measured using DPI method \u2013 Injection on VCC pin <\/td>\n<\/tr>\n | ||||||
82<\/td>\n | Figure D.5 \u2013 IB data for injection on VCC pin <\/td>\n<\/tr>\n | ||||||
83<\/td>\n | Annex E (normative) CIML Valid keywords and usage E.1 Root element keywords E.2 File header keywords Table E.1 \u2013 Root element keywords <\/td>\n<\/tr>\n | ||||||
84<\/td>\n | Table E.2 \u2013 Header section keywords <\/td>\n<\/tr>\n | ||||||
85<\/td>\n | E.3 Validity section keywords E.4 Global keywords Table E.3 \u2013 Validity section keywords <\/td>\n<\/tr>\n | ||||||
86<\/td>\n | E.5 Lead keyword E.6 Lead_definitions section attributes Table E.4 \u2013 Global keywords Table E.5 \u2013 Lead element definition <\/td>\n<\/tr>\n | ||||||
87<\/td>\n | E.7 Macromodels section attributes Table E.6 \u2013 Lead_definitions section keywords Table E.7 \u2013 Macromodels section keywords <\/td>\n<\/tr>\n | ||||||
88<\/td>\n | E.8 Pdn section keywords E.8.1 Lead element keywords Table E.8 \u2013 Lead element keywords in the Pdn section <\/td>\n<\/tr>\n | ||||||
90<\/td>\n | E.8.2 Netlist section keywords <\/td>\n<\/tr>\n | ||||||
91<\/td>\n | E.9 Ibc section keywords E.9.1 Lead element keywords Table E.9 \u2013 Netlist section keywords Table E.10 \u2013 Lead element keywords in the Ibc section <\/td>\n<\/tr>\n | ||||||
93<\/td>\n | E.9.2 Netlist section keywords E.10 Ib section keywords E.10.1 Lead element keywords <\/td>\n<\/tr>\n | ||||||
94<\/td>\n | Table E.11 \u2013 Lead element keywords in the Ib section <\/td>\n<\/tr>\n | ||||||
95<\/td>\n | E.10.2 Max_power_level section keywords E.10.3 Voltage section keywords Table E.12 \u2013 Max_power_level section keywords <\/td>\n<\/tr>\n | ||||||
96<\/td>\n | Table E.13 \u2013 Voltage section keywords <\/td>\n<\/tr>\n | ||||||
97<\/td>\n | E.10.4 Current section keywords Table E.14 \u2013 Current section keywords <\/td>\n<\/tr>\n | ||||||
98<\/td>\n | E.10.5 Power section keywords Table E.15 \u2013 Power section keywords <\/td>\n<\/tr>\n | ||||||
99<\/td>\n | E.10.6 Test_criteria section keywords <\/td>\n<\/tr>\n | ||||||
100<\/td>\n | Table E.16 \u2013 Test_criteria section keywords <\/td>\n<\/tr>\n | ||||||
101<\/td>\n | Annex F (informative) PDN impedance measurement methods using vector network analyzer F.1 General F.2 Conventional one-port method F.3 Two-port method for low impedance measurement Figure F.1 \u2013 Conventional one-port S-parameter measurement <\/td>\n<\/tr>\n | ||||||
102<\/td>\n | F.4 Two-port method for high impedance measurement Figure F.2 \u2013 Two-port method for low impedance measurement Figure F.3 \u2013 Two-port method for high impedance measurement <\/td>\n<\/tr>\n | ||||||
103<\/td>\n | Annex G (informative) RFIP measurement method description G.1 General G.2 Obtaining immunity parameters Figure G.1 \u2013 Test setup of the RFIP measurement method derived from DPI method Figure G.2 \u2013 Principle of the RFIP measurement method <\/td>\n<\/tr>\n | ||||||
105<\/td>\n | Annex H (informative) Immunity simulation with ICIM model based on pass\/fail test H.1 ICIM-CI macro-model of a voltage regulator IC H.1.1 General H.1.2 PDN extraction H.1.3 IB extraction Figure H.1 \u2013 Electrical schematic for extracting the voltage regulator\u2019s ICIM-CI <\/td>\n<\/tr>\n | ||||||
106<\/td>\n | H.1.4 SPICE-compatible macro-model H.2 Application level simulation and failure prediction Figure H.2 \u2013 ICIM-CI extraction on the voltage regulator example Figure H.3 \u2013 Example of a SPICE-compatible ICIM-CI macro-model of the voltage regulator <\/td>\n<\/tr>\n | ||||||
107<\/td>\n | Figure H.4 \u2013 Example of a board level simulation on the voltage regulator\u2019s ICIM-CI with PCB model and other components including parasitic elements Figure H.5 \u2013 Incident power as a function of frequency that is required to create a defect with a 10 nF filter <\/td>\n<\/tr>\n | ||||||
108<\/td>\n | Annex I (informative) Immunity simulation with ICIM model based on non pass\/fail test Figure I.1 \u2013 Example of an IB file for a given failure criterion <\/td>\n<\/tr>\n | ||||||
109<\/td>\n | Figure I.2 \u2013 Comparison of simulated transmitted power and measured immunity behaviour <\/td>\n<\/tr>\n | ||||||
110<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" EMC IC modelling – Models of integrated circuits for RF immunity behavioural simulation. Conducted immunity modelling (ICIM-CI)<\/b><\/p>\n |