{"id":194734,"date":"2024-10-19T12:21:24","date_gmt":"2024-10-19T12:21:24","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-802-3by-2016\/"},"modified":"2024-10-25T04:52:29","modified_gmt":"2024-10-25T04:52:29","slug":"ieee-802-3by-2016","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-802-3by-2016\/","title":{"rendered":"IEEE 802.3by 2016"},"content":{"rendered":"

Amendment Standard – Superseded. This amendment to IEEE Std 802.3-2015 adds Physical Layer (PHY) specifications and management parameters for 25 Gb\/s operation over twinaxial copper cabling (25GBASE-CR and 25GBASE-CR-S), electrical backplanes (25GBASE-KR and 25GBASE-KR-S), and multimode fiber (25GBASE-SR). This amendment also specifies a 25 Gigabit Attachment Unit Interface (25GAUI) and optional Energy Efficient Ethernet (EEE).<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nIEEE Std 802.3by-2016 Front cover <\/td>\n<\/tr>\n
2<\/td>\nTitle page <\/td>\n<\/tr>\n
4<\/td>\nImportant Notices and Disclaimers Concerning IEEE Standards Documents <\/td>\n<\/tr>\n
7<\/td>\nParticipants <\/td>\n<\/tr>\n
11<\/td>\nIntroduction <\/td>\n<\/tr>\n
14<\/td>\nContents <\/td>\n<\/tr>\n
28<\/td>\nIMPORTANT NOTICE <\/td>\n<\/tr>\n
29<\/td>\n1. Introduction
1.1 Overview
1.1.3 Architectural perspectives
1.1.3.2 Compatibility interfaces
1.3 Normative references
1.4 Definitions <\/td>\n<\/tr>\n
30<\/td>\n1.5 Abbreviations <\/td>\n<\/tr>\n
31<\/td>\n4. Media Access Control
4.4 Specific implementations
4.4.2 MAC parameters <\/td>\n<\/tr>\n
32<\/td>\n30. Management
30.3 Layer management for DTEs
30.3.2 PHY device managed object class
30.3.2.1 PHY device attributes
30.3.2.1.2 aPhyType
30.3.2.1.3 aPhyTypeList
30.3.2.1.5 aSymbolErrorDuringCarrier
30.5 Layer management for medium attachment units (MAUs)
30.5.1 MAU managed object class
30.5.1.1 MAU attributes
30.5.1.1.2 aMAUType <\/td>\n<\/tr>\n
33<\/td>\n30.5.1.1.4 aMediaAvailable
30.5.1.1.15 aFECAbility <\/td>\n<\/tr>\n
34<\/td>\n30.5.1.1.16 aFECMode
30.5.1.1.17 aFECCorrectedBlocks <\/td>\n<\/tr>\n
35<\/td>\n30.5.1.1.18 aFECUncorrectableBlocks
30.6 Management for link Auto-Negotiation
30.6.1 Auto-Negotiation managed object class
30.6.1.1 Auto-Negotiation attributes
30.6.1.1.5 aAutoNegLocalTechnologyAbility <\/td>\n<\/tr>\n
36<\/td>\n45. Management Data Input\/Output (MDIO) Interface
45.2 MDIO Interface Registers
45.2.1 PMA\/PMD registers <\/td>\n<\/tr>\n
37<\/td>\n45.2.1.1 PMA\/PMD control 1 register (Register 1.0)
45.2.1.1.3 Speed selection (1.0.13, 1.0.6, 1.0.5:2)
45.2.1.2 PMA\/PMD status 1 register (Register 1.1)
45.2.1.2.3 Fault (1.1.7) <\/td>\n<\/tr>\n
38<\/td>\n45.2.1.4 PMA\/PMD speed ability (Register 1.4)
45.2.1.4.a 25G capable (1.4.11)
45.2.1.6 PMA\/PMD control 2 register (Register 1.7) <\/td>\n<\/tr>\n
39<\/td>\n45.2.1.7 PMA\/PMD status 2 register (Register 1.8)
45.2.1.7.4 Transmit fault (1.8.11)
45.2.1.7.5 Receive fault (1.8.10)
45.2.1.8 PMD transmit disable register (Register 1.9) <\/td>\n<\/tr>\n
40<\/td>\n45.2.1.10 PMA\/PMD extended ability register (Register 1.11)
45.2.1.10.aa 25G extended abilities (1.11.12)
45.2.1.14 EEE capability (Register 1.16)
45.2.1.14.4a 25GBASE-R deep sleep (1.16.2)
45.2.3.4.5 25G capable (3.4.4) <\/td>\n<\/tr>\n
41<\/td>\n45.2.1.14b 25G PMA\/PMD extended ability register (Register 1.19)
45.2.1.14b.1 25GBASE-SR ability (1.19.4)
45.2.1.14b.2 25GBASE-CR ability (1.19.3)
45.2.1.14b.3 25GBASE-CR-S ability (1.19.2)
45.2.1.14b.4 25GBASE-KR ability (1.19.1) <\/td>\n<\/tr>\n
42<\/td>\n45.2.1.14b.5 25GBASE-KR-S ability (1.19.0)
45.2.1.80 BASE-R PMD control register (Register 1.150)
45.2.1.81 BASE-R PMD status register (Register 1.151)
45.2.1.82 BASE-R LP coefficient update, lane 0 register (Register 1.152)
45.2.1.83 BASE-R LP status report, lane 0 register (Register 1.153)
45.2.1.84 BASE-R LD coefficient update, lane 0 register (Register 1.154)
45.2.1.85 BASE-R LD status report, lane 0 register (Register 1.155) <\/td>\n<\/tr>\n
43<\/td>\n45.2.1.94 Single-lane PHY 10GBASE-R FEC corrected blocks counter (Register 1.172, 1.173)
45.2.1.95 Single-lane PHY 10GBASE-R FEC uncorrected blocks counter (Register 1.174, 1.175)
45.2.1.96 CAUI-4 chip-to-moduleC2M and 25GAUI C2M recommended CTLE register (Register 1.179)
45.2.1.96.1 Recommended CTLE peaking (1.179.4:1)
45.2.1.97 25GAUI C2C and lane 0 CAUI-4 chip-to-chipC2C transmitter equalization, receive direction, lane 0 register (Register 1.180) <\/td>\n<\/tr>\n
44<\/td>\n45.2.1.97.1 Request flag (1.180.15)
45.2.1.97.2 Post-cursor request (1.180.14:12)
45.2.1.97.3 Pre-cursor request (1.180.11:10)
45.2.1.97.4 Post-cursor remote setting (1.180.9:7)
45.2.1.97.5 Pre-cursor remote setting (1.180.6:5)
45.2.1.97.6 Post-cursor local setting (1.180.4:2)
45.2.1.97.7 Pre-cursor local setting (1.180.1:0) <\/td>\n<\/tr>\n
45<\/td>\n45.2.1.99 25GAUI C2C and lane 0 CAUI-4 chip-to-chipC2C transmitter equalization, transmit direction, lane 0 register (Register 1.184)
45.2.1.99.1 Request flag (1.184.15)
45.2.1.99.2 Post-cursor request (1.184.14:12)
45.2.1.99.3 Pre-cursor request (1.184.11:10)
45.2.1.99.4 Post-cursor remote setting (1.184.9:7)
45.2.1.99.5 Pre-cursor remote setting (1.184.6:5) <\/td>\n<\/tr>\n
46<\/td>\n45.2.1.99.6 Post-cursor local setting (1.184.4:2)
45.2.1.99.7 Pre-cursor local setting (1.184.1:0)
45.2.1.101 RS-FEC control register (Register 1.200)
45.2.1.101.a 25G RS-FEC enable (1.200.2)
45.2.1.101.1 FEC bypass indication enable (1.200.1)
45.2.1.101.2 FEC bypass correction enable (1.200.0) <\/td>\n<\/tr>\n
47<\/td>\n45.2.1.102 RS-FEC status register (Register 1.201)
45.2.1.102.1 PCS align status (1.201.15)
45.2.1.102.2 RS-FEC align status (1.201.14)
45.2.1.102.7 RS-FEC high SER (1.201.2)
45.2.1.102.8 FEC bypass indication ability (1.201.1)
45.2.1.102.9 FEC bypass correction ability (1.201.0) <\/td>\n<\/tr>\n
48<\/td>\n45.2.1.103 RS-FEC corrected codewords counter (Register 1.202, 1.203)
45.2.1.104 RS-FEC uncorrected codewords counter (Register 1.204, 1.205)
45.2.1.106 RS-FEC symbol error counter lane 0 (Register 1.210, 1.211)
45.2.3 PCS registers
45.2.3.1 PCS control 1 register (Register 3.0) <\/td>\n<\/tr>\n
49<\/td>\n45.2.3.2 PCS status 1 register (Register 3.1)
45.2.3.2.7 PCS receive link status (3.1.2)
45.2.3.4 PCS speed ability (Register 3.4)
45.2.3.6 PCS control 2 register (Register 3.7) <\/td>\n<\/tr>\n
50<\/td>\n45.2.3.6.1 PCS type selection (3.7.2:0)
45.2.3.7 PCS status 2 register (Register 3.8)
45.2.3.7.3a 25GBASE-R capable (3.8.7)
45.2.3.9 EEE control and capability (Register 3.20) <\/td>\n<\/tr>\n
51<\/td>\n45.2.3.9.2a 25GBASE-R deep sleep (3.20.11)
45.2.3.9.2b 25GBASE-R fast wake (3.20.10)
45.2.3.13 BASE-R and 10GBASE-T PCS status 1 register (Register 3.32)
45.2.3.13.1 BASE-R and 10GBASE-T receive link status (3.32.12)
45.2.3.13.4 BASE-R and 10GBASE-T PCS high BER (3.32.1)
45.2.3.13.5 BASE-R and 10GBASE-T PCS block lock (3.32.0)
45.2.3.14 BASE-R and 10GBASE-T PCS status 2 register (Register 3.33)
45.2.3.14.1 Latched block lock (3.33.15) <\/td>\n<\/tr>\n
52<\/td>\n45.2.3.14.2 Latched high BER (3.33.14)
45.2.3.14.3 BER (3.33.13:8)
45.2.3.14.4 Errored blocks (3.33.7:0)
45.2.3.15 10\/25GBASE-R PCS test pattern seed A (Registers 3.34 through 3.37)
45.2.3.16 10\/25GBASE-R PCS test pattern seed B (Registers 3.38 through 3.41)
45.2.3.17 BASE-R PCS test-pattern control register (Register 3.42) <\/td>\n<\/tr>\n
53<\/td>\n45.2.7 Auto-Negotiation registers
45.2.7.12 Backplane Ethernet, BASE-R copper status (Register 7.48) <\/td>\n<\/tr>\n
54<\/td>\n45.2.7.12.1a RS-FEC negotiated (7.48.7)
45.2.7.12.2 Negotiated Port Type (7.48.1, 7.48.2, 7.48.3, 7.48.5, 7.48.6, 7.48.8, 7.48.9, 7.48.10, 7.48.11, 7.48.12, 7.48.13)
45.2.7.13 EEE advertisement (Register 7.60)
45.2.7.13.a 25GBASE-R EEE supported (7.60.14) <\/td>\n<\/tr>\n
55<\/td>\n45.2.7.14 EEE link partner ability (Register 7.61) <\/td>\n<\/tr>\n
56<\/td>\n45.5 Protocol implementation conformance statement (PICS) proforma for Clause 45, Management Data Input\/Output (MDIO) interface
45.5.3 PICS proforma tables for the Management Data Input Output (MDIO) interface
45.5.3.3 PMA\/PMD management functions <\/td>\n<\/tr>\n
57<\/td>\n69. Introduction to Ethernet operation over electrical backplanes
69.1 Overview
69.1.1 Scope
69.1.2 Relationship of Backplane Ethernet to the ISO OSI reference model <\/td>\n<\/tr>\n
59<\/td>\n69.2 Summary of Backplane Ethernet Sublayers
69.2.1 Reconciliation sublayer and media independent interfaces
69.2.3 Physical Layer signaling systems <\/td>\n<\/tr>\n
60<\/td>\n69.3 Delay constraints
69.5 Protocol implementation conformance statement (PICS) proforma <\/td>\n<\/tr>\n
61<\/td>\n73. Auto-Negotiation for backplane and copper cable assembly
73.2 Relationship to the ISO\/IEC Open Systems Interconnection (OSI) reference model
73.3 Functional specifications <\/td>\n<\/tr>\n
62<\/td>\n73.6 Link codeword encoding
73.6.4 Technology Ability Field <\/td>\n<\/tr>\n
63<\/td>\n73.6.5 FEC capability
73.6.5.1 FEC resolution for 25G PHYs
73.6.5.2 FEC resolution for 10 Gb\/s per lane PHYs <\/td>\n<\/tr>\n
64<\/td>\n73.6.5.3 FEC control variables
73.7 Receive function requirements
73.7.1 DME page reception
73.7.6 Priority Resolution function <\/td>\n<\/tr>\n
65<\/td>\n73.6 Management register requirements
73.10 State diagrams and variable definitions
73.10.1 State diagram variables <\/td>\n<\/tr>\n
67<\/td>\n74. Forward Error Correction (FEC) sublayer for BASE-R PHYs
74.1 Overview <\/td>\n<\/tr>\n
68<\/td>\n74.3 Relationship to other sublayers
74.4 Inter-sublayer interfaces <\/td>\n<\/tr>\n
69<\/td>\n74.4.1a Functional block diagram for 25GBASE-R PHYs <\/td>\n<\/tr>\n
70<\/td>\n74.5 FEC service interface
74.5.1a 25GBASE-R service primitives <\/td>\n<\/tr>\n
71<\/td>\n74.6 Delay constraints
74.7 FEC principle of operation
74.7.4 Functions within FEC sublayer
74.7.4.1 Reverse gearbox function
74.7.4.1.2 Reverse gearbox function for 25GBASE-R, 40GBASE-R, and 100GBASE-R <\/td>\n<\/tr>\n
72<\/td>\n74.7.4.3 FEC transmission bit ordering <\/td>\n<\/tr>\n
73<\/td>\n74.7.4.4 FEC (2112,2080) encoder
74.7.4.5 FEC decoder <\/td>\n<\/tr>\n
74<\/td>\n74.7.4.5.1 FEC (2112,2080) decoding <\/td>\n<\/tr>\n
75<\/td>\n74.7.4.6 FEC receive bit ordering <\/td>\n<\/tr>\n
76<\/td>\n74.7.4.8 FEC rapid block synchronization for EEE (optional) <\/td>\n<\/tr>\n
77<\/td>\n74.8 FEC MDIO function mapping
74.8.1 FEC capability
74.9 BASE-R PHY test-pattern mode <\/td>\n<\/tr>\n
78<\/td>\n74.11 Protocol implementation conformance statement (PICS) proforma for Clause 74, Forward Error Correction (FEC) sublayer for BASE-R PHYs
74.11.3 Major capabilities\/options
74.11.5 FEC Requirements <\/td>\n<\/tr>\n
79<\/td>\n78. Energy-Efficient Ethernet (EEE)
78.1 Overview
78.1.1 LPI Signaling
78.1.3 Reconciliation sublayer operation
78.1.3.3 PHY LPI operation
78.1.3.3.1 PHY LPI transmit operation <\/td>\n<\/tr>\n
80<\/td>\n78.1.4 PHY types optionally supporting EEE
78.2 LPI mode timing parameters description
78.5 Communication link access latency <\/td>\n<\/tr>\n
81<\/td>\n78.5.2 25 Gb\/s, 40 Gb\/s, and 100 Gb\/s PHY extension using 25GAUI, XLAUI, or CAUI-n <\/td>\n<\/tr>\n
82<\/td>\n90. Ethernet support for time synchronization protocols
90.1 Introduction <\/td>\n<\/tr>\n
83<\/td>\n105. Introduction to 25 Gb\/s networks
105.1 Overview
105.1.1 Scope
105.1.2 Relationship of 25 Gigabit Ethernet to the ISO OSI reference model
105.1.3 Nomenclature <\/td>\n<\/tr>\n
85<\/td>\n105.2 Physical Layer signaling systems
105.3 Summary of 25 Gigabit Ethernet sublayers
105.3.1 Reconciliation Sublayer (RS) and 25 Gigabit Media Independent Interface (25GMII) <\/td>\n<\/tr>\n
86<\/td>\n105.3.2 Physical Coding Sublayer (PCS)
105.3.3 Forward Error Correction (FEC) sublayer
105.3.4 Physical Medium Attachment (PMA) sublayer
105.3.5 Physical Medium Dependent (PMD) sublayer
105.3.6 Auto-Negotiation (AN)
105.3.7 Management interface (MDIO\/MDC)
105.3.8 Management <\/td>\n<\/tr>\n
87<\/td>\n105.4 Service interface specification method and notation
105.4.1 Inter-sublayer service interface
105.4.2 Instances of the Inter-sublayer service interface <\/td>\n<\/tr>\n
88<\/td>\n105.4.3 Semantics of inter-sublayer service interface primitives
105.4.3.1 IS_UNITDATA.request
105.4.3.1.1 Semantics of the service primitive
105.4.3.1.2 When generated
105.4.3.1.3 Effect of receipt
105.4.3.2 IS_UNITDATA.indication
105.4.3.2.1 Semantics of the service primitive <\/td>\n<\/tr>\n
89<\/td>\n105.4.3.2.2 When generated
105.4.3.2.3 Effect of receipt <\/td>\n<\/tr>\n
90<\/td>\n105.4.3.3 IS_SIGNAL.indication
105.4.3.3.1 Semantics of the service primitive <\/td>\n<\/tr>\n
91<\/td>\n105.4.3.3.2 When generated
105.4.3.3.3 Effect of receipt
105.4.3.4 IS_TX_MODE.request
105.4.3.4.1 Semantics of the service primitive
105.4.3.4.2 When generated
105.4.3.4.3 Effect of receipt
105.4.3.5 IS_RX_MODE.request
105.4.3.5.1 Semantics of the service primitive
105.4.3.5.2 When generated <\/td>\n<\/tr>\n
92<\/td>\n105.4.3.5.3 Effect of receipt
105.4.3.6 IS_RX_LPI_ACTIVE.request
105.4.3.6.1 Semantics of the service primitive
105.4.3.6.2 When generated
105.4.3.6.3 Effect of receipt
105.4.3.7 IS_ENERGY_DETECT.indication
105.4.3.7.1 Semantics of the service primitive
105.4.3.7.2 When generated
105.4.3.7.3 Effect of receipt <\/td>\n<\/tr>\n
93<\/td>\n105.4.3.8 IS_RX_TX_MODE.indication
105.4.3.8.1 Semantics of the service primitive
105.4.3.8.2 When generated
105.4.3.8.3 Effect of receipt
105.5 Delay constraints
105.6 State diagrams <\/td>\n<\/tr>\n
94<\/td>\n105.7 Protocol implementation conformance statement (PICS) proforma <\/td>\n<\/tr>\n
95<\/td>\n106. Reconciliation Sublayer (RS) and Media Independent Interface (25GMII) for 25 Gb\/s operation
106.1 Overview <\/td>\n<\/tr>\n
96<\/td>\n106.1.1 Summary of major concepts
106.1.2 Application
106.1.3 Rate of operation
106.1.4 Delay constraints <\/td>\n<\/tr>\n
97<\/td>\n106.1.5 Allocation of functions
106.1.6 25GMII structure
106.1.7 Mapping of 25GMII signals to PLS service primitives
106.1.7.1 Mapping of PLS_DATA.request
106.1.7.2 Mapping of PLS_DATA.indication
106.1.7.3 Mapping of PLS_CARRIER.indication
106.1.7.4 Mapping of PLS_SIGNAL.indication <\/td>\n<\/tr>\n
98<\/td>\n106.1.7.5 Mapping of PLS_DATA_VALID.indication
106.2 25GMII data stream
106.3 25GMII functional specifications
106.4 LPI Assertion and Detection <\/td>\n<\/tr>\n
99<\/td>\n106.5 Protocol implementation conformance statement (PICS) proforma for Clause 106 Reconciliation Sublayer (RS) and Media Independent Interface (25GMII) for 25 Gb\/s operation
106.5.1 Introduction
106.5.2 Identification
106.5.2.1 Implementation identification
106.5.2.2 Protocol summary <\/td>\n<\/tr>\n
100<\/td>\n106.5.2.3 Major capabilities\/options
106.5.3 PICS proforma Tables for Reconciliation Sublayer and 25 Gigabit Media Independent Interface
106.5.3.1 General
106.5.3.2 Mapping of PLS service primitives
106.5.3.3 25GMII signal functional specifications. <\/td>\n<\/tr>\n
101<\/td>\n107. Physical Coding Sublayer (PCS) for 64B\/66B, type 25GBASE-R
107.1 Overview
107.1.1 Scope
107.1.2 Relationship of 25GBASE-R to other standards
107.1.3 Summary of 25GBASE-R sublayers
107.1.3.1 Physical Coding Sublayer (PCS)
107.1.4 Inter-sublayer interfaces <\/td>\n<\/tr>\n
102<\/td>\n107.1.4.1 PCS service interface (25GMII)
107.1.4.2 Physical Medium Attachment (PMA) service interface
107.2 Functions within the PCS <\/td>\n<\/tr>\n
103<\/td>\n107.2.1 Notation conventions
107.2.2 Transmission order <\/td>\n<\/tr>\n
104<\/td>\n107.2.3 Test-pattern generator
107.3 LPI <\/td>\n<\/tr>\n
105<\/td>\n107.3 Delay constraints
107.4 Support for Auto-Negotiation <\/td>\n<\/tr>\n
106<\/td>\n107.5 Protocol implementation conformance statement (PICS) proforma for Clause 107, Physical Coding Sublayer (PCS) for 64B\/66B, type 25GBASE-R
107.5.1 Introduction
107.5.2 Identification
107.5.2.1 Implementation identification
107.5.2.2 Protocol summary <\/td>\n<\/tr>\n
107<\/td>\n107.5.3 Major capabilities\/options
107.5.4 25G PCS
107.5.4.1 Clause 49 functionality
107.5.4.2 Test-pattern generator
107.5.4.3 LPI <\/td>\n<\/tr>\n
108<\/td>\n107.5.4.4 Delay Constraints <\/td>\n<\/tr>\n
109<\/td>\n108. Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 25GBASE-R PHYs
108.1 Overview
108.1.1 Scope
108.1.2 Position of RS-FEC in the 25GBASE-R PHY sublayers
108.2 FEC service interface <\/td>\n<\/tr>\n
110<\/td>\n108.3 PMA compatibility <\/td>\n<\/tr>\n
111<\/td>\n108.4 Delay constraints
108.5 Functions within the 25GBASE-R RS-FEC sublayer
108.5.1 Functional block diagram
108.5.2 Transmit function
108.5.2.1 Block synchronization
108.5.2.2 Rate compensation for codeword markers in the transmit direction
108.5.2.3 64B\/66B to 256B\/257B transcoder <\/td>\n<\/tr>\n
113<\/td>\n108.5.2.4 Codeword marker insertion
108.5.2.5 Reed-Solomon encoder
108.5.2.6 Codeword serialization
108.5.2.7 RS-FEC encoding for rapid codeword lock (EEE deep sleep) <\/td>\n<\/tr>\n
115<\/td>\n108.5.3 Receive function
108.5.3.1 Codeword marker lock
108.5.3.2 Reed-Solomon decoder <\/td>\n<\/tr>\n
116<\/td>\n108.5.3.3 Codeword monitor <\/td>\n<\/tr>\n
117<\/td>\n108.5.3.4 Codeword marker removal
108.5.3.5 256B\/257B to 64B\/66B transcoder
108.5.3.6 Rate compensation for codeword markers in the receive direction
108.5.3.7 Rapid codeword lock for EEE deep sleep <\/td>\n<\/tr>\n
118<\/td>\n108.5.3.8 Receive bit ordering
108.5.4 Detailed functions and state diagrams
108.5.4.1 State diagram conventions
108.5.4.2 State variables <\/td>\n<\/tr>\n
120<\/td>\n108.5.4.3 Functions
108.5.4.4 Counters <\/td>\n<\/tr>\n
121<\/td>\n108.5.4.5 Timers <\/td>\n<\/tr>\n
122<\/td>\n108.5.4.6 State diagrams <\/td>\n<\/tr>\n
123<\/td>\n108.6 25GBASE-R RS-FEC MDIO function mapping <\/td>\n<\/tr>\n
124<\/td>\n108.6.1 FEC_bypass_correction_enable
108.6.2 FEC_bypass_indication_enable <\/td>\n<\/tr>\n
125<\/td>\n108.6.3 25G RS-FEC Enable
108.6.4 FEC_bypass_correction_ability
108.6.5 FEC_bypass_indication_ability
108.6.6 FEC_high_ser
108.6.7 FEC_corrected_cw_counter
108.6.8 FEC_uncorrected_cw_counter <\/td>\n<\/tr>\n
126<\/td>\n108.6.9 FEC_symbol_error_counter_0
108.6.10 align_status <\/td>\n<\/tr>\n
127<\/td>\n108.7 Protocol implementation conformance statement (PICS) proforma for Clause 108, Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 25GBASE-R PHYs
108.7.1 Introduction
108.7.2 Identification
108.7.2.1 Implementation identification
108.7.2.2 Protocol summary <\/td>\n<\/tr>\n
128<\/td>\n108.7.3 Major capabilities\/options
108.7.4 PICS proforma tables for Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 25GBASE-R PHYs
108.7.4.1 Transmit function <\/td>\n<\/tr>\n
129<\/td>\n108.7.4.2 Receive function <\/td>\n<\/tr>\n
130<\/td>\n108.7.4.3 State diagrams
108.7.4.4 MDIO function mapping <\/td>\n<\/tr>\n
131<\/td>\n109. Physical Medium Attachment (PMA) sublayer, type 25GBASE-R
109.1 Overview
109.1.1 Scope
109.1.2 Position of the PMA in the 25GBASE-R sublayers <\/td>\n<\/tr>\n
132<\/td>\n109.1.3 Summary of functions <\/td>\n<\/tr>\n
133<\/td>\n109.1.4 PMA sublayer positioning <\/td>\n<\/tr>\n
134<\/td>\n109.2 PMA service interface <\/td>\n<\/tr>\n
135<\/td>\n109.3 Service interface below PMA <\/td>\n<\/tr>\n
136<\/td>\n109.4 Functions within the PMA
109.4.1 Signal drivers
109.4.2 PMA local loopback mode
109.4.3 PMA remote loopback mode
109.4.4 PMA test patterns <\/td>\n<\/tr>\n
137<\/td>\n109.4.4.1 Transmit PRBS31 test-pattern generation
109.4.4.2 Receive PRBS31 test-pattern generation
109.4.4.3 Transmit PRBS31 test-pattern checking <\/td>\n<\/tr>\n
138<\/td>\n109.4.4.4 Receive PRBS31 test-pattern checking
109.4.4.5 Transmit PRBS9 test-pattern generation
109.4.4.6 Receive PRBS9 test-pattern generation
109.4.4.7 Transmit square wave test-pattern generation <\/td>\n<\/tr>\n
139<\/td>\n109.4.5 Energy Efficient Ethernet for 25GAUI
109.5 Delay constraints
109.6 PMA MDIO function mapping <\/td>\n<\/tr>\n
142<\/td>\n109.7 Protocol implementation conformance statement (PICS) proforma for Clause 109, Physical Medium Attachment (PMA) sublayer, type 25GBASE-R
109.7.1 Introduction
109.7.2 Identification
109.7.2.1 Implementation identification
109.7.2.2 Protocol summary <\/td>\n<\/tr>\n
143<\/td>\n109.7.3 PICS proforma tables for the 25GBASE-R PMA Sublayer
109.7.4 Major capabilities\/options
109.7.4.1 PMA functions <\/td>\n<\/tr>\n
144<\/td>\n109.7.4.2 PMA characteristics <\/td>\n<\/tr>\n
145<\/td>\n110. Physical Medium Dependent (PMD) sublayer and baseband medium, type 25GBASE-CR and 25GBASE-CR-S
110.1 Overview <\/td>\n<\/tr>\n
146<\/td>\n110.2 PMD service interface <\/td>\n<\/tr>\n
147<\/td>\n110.3 PCS requirements for Auto-Negotiation (AN) service interface
110.4 Delay constraints <\/td>\n<\/tr>\n
148<\/td>\n110.5 PMD MDIO function mapping
110.6 FEC modes <\/td>\n<\/tr>\n
149<\/td>\n110.7 PMD functional specifications
110.7.1 Link block diagram <\/td>\n<\/tr>\n
150<\/td>\n110.7.2 PMD transmit function <\/td>\n<\/tr>\n
151<\/td>\n110.7.3 PMD receive function
110.7.4 Global PMD signal detect function
110.7.5 Global PMD transmit disable function <\/td>\n<\/tr>\n
152<\/td>\n110.7.6 Loopback mode
110.7.7 PMD fault function
110.7.8 PMD transmit fault function
110.7.9 PMD receive fault function
110.7.10 PMD control function
110.8 Electrical characteristics
110.8.1 Signal levels <\/td>\n<\/tr>\n
153<\/td>\n110.8.2 Signal paths
110.8.3 Transmitter characteristics
110.8.4 Receiver characteristics
110.8.4.1 Receiver input amplitude tolerance
110.8.4.2 Receiver interference tolerance test <\/td>\n<\/tr>\n
155<\/td>\n110.8.4.2.1 Test setup
110.8.4.2.2 Test channel
110.8.4.2.3 Test channel calibration <\/td>\n<\/tr>\n
157<\/td>\n110.8.4.2.4 Pattern generator and noise injection
110.8.4.2.5 Test procedure
110.8.4.3 Receiver jitter tolerance <\/td>\n<\/tr>\n
158<\/td>\n110.8.4.4 Signaling rate range
110.9 Channel characteristics
110.10 Cable assembly characteristics <\/td>\n<\/tr>\n
159<\/td>\n110.10.1 Characteristic impedance and reference impedance
110.10.2 Cable assembly insertion loss
110.10.3 Cable assembly differential return loss <\/td>\n<\/tr>\n
160<\/td>\n110.10.4 Differential to common-mode return loss
110.10.5 Differential to common-mode conversion loss
110.10.6 Common-mode to common-mode return loss
110.10.7 Cable assembly Channel Operating Margin <\/td>\n<\/tr>\n
161<\/td>\n110.10.7.1 Channel signal and crosstalk path calculations <\/td>\n<\/tr>\n
162<\/td>\n110.10.7.1.1 Channel signal path
110.10.7.1.2 Channel crosstalk paths <\/td>\n<\/tr>\n
163<\/td>\n110.10.7.2 Signal and crosstalk paths used in calculation of COM
110.10.7.2.1 SFP28 to SFP28
110.10.7.2.2 QSFP28 to SFP28
110.10.7.2.3 SFP28 to QSFP28 <\/td>\n<\/tr>\n
164<\/td>\n110.10.7.2.4 QSFP28 to QSFP28
110.11 MDI specification
110.11.1 Single-lane MDI connectors <\/td>\n<\/tr>\n
165<\/td>\n110.12 Environmental specifications <\/td>\n<\/tr>\n
166<\/td>\n110.13 Protocol implementation conformance statement (PICS) proforma for Clause 110, Physical Medium Dependent (PMD) sublayer and baseband medium, type 25GBASE-CR and 25GBASE-CR-S
110.13.1 Introduction
110.13.2 Identification
110.13.2.1 Implementation identification
110.13.2.2 Protocol summary <\/td>\n<\/tr>\n
167<\/td>\n110.13.3 Major capabilities\/options <\/td>\n<\/tr>\n
168<\/td>\n110.13.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and baseband medium, type 25GBASE-CR and 25GBASE-CR-S
110.13.4.1 PMD functional specifications <\/td>\n<\/tr>\n
169<\/td>\n110.13.4.2 Management functions
110.13.4.3 Transmitter specifications <\/td>\n<\/tr>\n
171<\/td>\n110.13.4.4 Receiver specifications <\/td>\n<\/tr>\n
172<\/td>\n110.13.4.5 Cable assembly specifications
110.13.4.6 MDI connector specifications <\/td>\n<\/tr>\n
173<\/td>\n110.13.4.7 Environmental specifications <\/td>\n<\/tr>\n
174<\/td>\n111. Physical Medium Dependent (PMD) sublayer and baseband medium, type 25GBASE-KR and 25GBASE-KR-S
111.1 Overview <\/td>\n<\/tr>\n
175<\/td>\n111.2 PMD service interface <\/td>\n<\/tr>\n
176<\/td>\n111.3 PCS requirements for Auto-Negotiation (AN) service interface
111.4 Delay constraints
111.5 PMD MDIO function mapping <\/td>\n<\/tr>\n
177<\/td>\n111.6 FEC modes <\/td>\n<\/tr>\n
178<\/td>\n111.7 PMD functional specifications
111.7.1 Link block diagram
111.7.2 PMD transmit function <\/td>\n<\/tr>\n
179<\/td>\n111.7.3 PMD receive function
111.7.4 Global PMD signal detect function
111.7.5 Global PMD transmit disable function
111.7.6 Loopback mode <\/td>\n<\/tr>\n
180<\/td>\n111.7.7 PMD fault function
111.7.8 PMD transmit fault function
111.7.9 PMD receive fault function
111.7.10 PMD control function
111.8 Electrical characteristics
111.8.1 MDI <\/td>\n<\/tr>\n
181<\/td>\n111.8.2 Transmitter characteristics
111.8.3 Receiver characteristics
111.8.3.1 Receiver interference tolerance <\/td>\n<\/tr>\n
183<\/td>\n111.8.3.2 Receiver jitter tolerance <\/td>\n<\/tr>\n
184<\/td>\n111.9 Channel characteristics
111.9.1 25GBASE-KR channel
111.9.2 25GBASE-KR-S channel <\/td>\n<\/tr>\n
185<\/td>\n111.10 Environmental specifications <\/td>\n<\/tr>\n
186<\/td>\n111.11 Protocol implementation conformance statement (PICS) proforma for Clause 111, Physical Medium Dependent (PMD) sublayer and baseband medium, type 25GBASE-KR and 25GBASE-KR-S
111.11.1 Introduction
111.11.2 Identification
111.11.2.1 Implementation identification
111.11.2.2 Protocol summary <\/td>\n<\/tr>\n
187<\/td>\n111.11.3 Major capabilities\/options <\/td>\n<\/tr>\n
188<\/td>\n111.11.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and baseband medium, type 25GBASE-KR and 25GBASE-KR-S
111.11.4.1 Functional specifications <\/td>\n<\/tr>\n
189<\/td>\n111.11.4.2 Transmitter characteristics <\/td>\n<\/tr>\n
191<\/td>\n111.11.4.3 Receiver characteristics
111.11.4.4 Channel characteristics <\/td>\n<\/tr>\n
192<\/td>\n111.11.4.5 Environmental specifications <\/td>\n<\/tr>\n
193<\/td>\n112. Physical Medium Dependent (PMD) sublayer and medium, type 25GBASE-SR
112.1 Overview <\/td>\n<\/tr>\n
194<\/td>\n112.1.1 Bit error ratio
112.2 Physical Medium Dependent (PMD) service interface <\/td>\n<\/tr>\n
195<\/td>\n112.3 Delay constraints
112.4 PMD MDIO function mapping <\/td>\n<\/tr>\n
196<\/td>\n112.5 PMD functional specifications
112.5.1 PMD block diagram <\/td>\n<\/tr>\n
197<\/td>\n112.5.2 PMD transmit function
112.5.3 PMD receive function
112.5.4 PMD global signal detect function <\/td>\n<\/tr>\n
198<\/td>\n112.5.5 PMD reset function
112.5.6 PMD global transmit disable function (optional)
112.5.7 PMD fault function (optional)
112.5.8 PMD transmit fault function (optional)
112.5.9 PMD receive fault function (optional)
112.6 PMD to MDI optical specifications for 25GBASE-SR <\/td>\n<\/tr>\n
199<\/td>\n112.6.1 25GBASE-SR transmitter optical specifications
112.6.2 25GBASE-SR receive optical specifications
112.6.3 25GBASE-SR illustrative link power budget
112.7 Definition of optical parameters and measurement methods
112.7.1 Test patterns for optical parameters <\/td>\n<\/tr>\n
200<\/td>\n112.7.2 Center wavelength and spectral width
112.7.3 Average optical power
112.7.4 Optical Modulation Amplitude (OMA)
112.7.5 Transmitter and dispersion eye closure (TDEC)
112.7.6 Extinction ratio
112.7.7 Transmitter optical waveform (transmit eye)
112.7.8 Stressed receiver sensitivity
112.8 Safety, installation, environment, and labeling
112.8.1 General safety <\/td>\n<\/tr>\n
201<\/td>\n112.8.2 Laser safety
112.8.3 Installation
112.8.4 Environment
112.8.5 Electromagnetic emission
112.8.6 Temperature, humidity, and handling
112.8.7 PMD labeling requirements <\/td>\n<\/tr>\n
202<\/td>\n112.9 Fiber optic cabling model
112.10 Characteristics of the fiber optic cabling (channel)
112.10.1 Optical fiber cable
112.10.2 Optical fiber connection <\/td>\n<\/tr>\n
203<\/td>\n112.10.2.1 Connection insertion loss
112.10.2.2 Maximum discrete reflectance
112.10.3 Medium Dependent Interface (MDI) <\/td>\n<\/tr>\n
204<\/td>\n112.11 Protocol implementation conformance statement (PICS) proforma for Clause 112, Physical Medium Dependent (PMD) sublayer and medium, type 25GBASE-SR
112.11.1 Introduction
112.11.2 Identification
112.11.2.1 Implementation identification
112.11.2.2 Protocol summary <\/td>\n<\/tr>\n
205<\/td>\n112.11.3 Major capabilities\/options
112.11.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, type 25GBASE-SR
112.11.4.1 PMD functional specifications <\/td>\n<\/tr>\n
206<\/td>\n112.11.4.2 Management functions
112.11.4.3 PMD to MDI optical specifications for 25GBASE-SR <\/td>\n<\/tr>\n
207<\/td>\n112.11.4.4 Optical measurement methods
112.11.4.5 Environmental specifications
112.11.4.6 Characteristics of the fiber optic cabling and MDI <\/td>\n<\/tr>\n
208<\/td>\nAnnex 4A (normative) Simplified full duplex media access control
4A.4 Specific implementations
4A.4.2 MAC parameters <\/td>\n<\/tr>\n
209<\/td>\nAnnex 31B (normative) MAC Control PAUSE operation <\/td>\n<\/tr>\n
211<\/td>\nAnnex 93A (normative) Specification methods for electrical channels
93A.1 Channel Operating Margin <\/td>\n<\/tr>\n
212<\/td>\n93A.1.4 Filters
93A.2 Test channel calibration using COM <\/td>\n<\/tr>\n
213<\/td>\nAnnex 109A (normative) Chip-to-chip 25 Gigabit Attachment Unit Interface (25GAUI C2C)
109A.1 Overview <\/td>\n<\/tr>\n
214<\/td>\n109A.2 25GAUI C2C compliance point definition
109A.3 25GAUI C2C electrical characteristics
109A.3.1 25GAUI C2C transmitter characteristics
109A.3.2 25GAUI C2C receiver characteristics
109A.3.3 Optional EEE operation
109A.4 25GAUI C2C channel characteristics <\/td>\n<\/tr>\n
215<\/td>\n109A.5 Protocol implementation conformance statement (PICS) proforma for Annex 109A, Chip-to-chip 25 Gigabit Attachment Unit Interface (25GAUI C2C)
109A.5.1 Introduction
109A.5.2 Identification
109A.5.2.1 Implementation identification
109A.5.2.2 Protocol summary <\/td>\n<\/tr>\n
216<\/td>\n109A.5.3 Major capabilities\/options
109A.5.4 PICS proforma tables for chip-to-chip 25 Gigabit Attachment Unit Interface (25GAUI C2C)
109A.5.4.1 Transmitter <\/td>\n<\/tr>\n
217<\/td>\n109A.5.4.2 Receiver
109A.5.4.3 Channel <\/td>\n<\/tr>\n
218<\/td>\nAnnex 109B (normative) Chip-to-module 25 Gigabit Attachment Unit Interface (25GAUI C2M)
109B.1 Overview <\/td>\n<\/tr>\n
219<\/td>\n109B.1.1 Bit error ratio
109B.2 25GAUI C2M compliance point definitions
109B.3 25GAUI C2M electrical characteristics
109B.3.1 25GAUI C2M host output characteristics
109B.3.2 25GAUI C2M module output characteristics <\/td>\n<\/tr>\n
220<\/td>\n109B.3.2.1 25GAUI C2M module output eye opening
109B.3.2.1.1 Eye opening using measurement method A
109B.3.2.1.2 Eye opening using measurement method B
109B.3.3 25GAUI C2M host input characteristics
109B.3.4 25GAUI C2M module input characteristics <\/td>\n<\/tr>\n
221<\/td>\n109B.3.4.1 Module stressed input test using measurement method A
109B.3.4.2 Module stressed input test using measurement method B
109B.4 25GAUI C2M measurement methodology
109B.4.1 Eye width, eye height, and eye closure measurement method B <\/td>\n<\/tr>\n
223<\/td>\n109B.5 Protocol implementation conformance statement (PICS) proforma for Annex 109B, Chip-to-module 25 Gigabit Attachment Unit Interface (25GAUI C2M)
109B.5.1 Introduction
109B.5.2 Identification
109B.5.2.1 Implementation identification
109B.5.2.2 Protocol summary <\/td>\n<\/tr>\n
224<\/td>\n109B.5.3 Major capabilities\/options
109B.5.4 PICS proforma tables for chip-to-module 25 Gigabit Attachment Unit Interface (25GAUI C2M)
109B.5.3.1 Host output <\/td>\n<\/tr>\n
225<\/td>\n109B.5.4.2 Module output
109B.5.4.3 Host input <\/td>\n<\/tr>\n
226<\/td>\n109B.5.4.4 Module input <\/td>\n<\/tr>\n
227<\/td>\nAnnex 109C (informative) 25GBASE-R PMA sublayer partitioning examples <\/td>\n<\/tr>\n
231<\/td>\nAnnex 110A (informative) TP0 and TP5 test point parameters and channel characteristics for 25GBASE-CR and 25GBASE-CR-S
110A.1 Overview
110A.2 Transmitter characteristics at TP0
110A.3 Receiver characteristics at TP5
110A.4 Transmitter and receiver differential printed circuit board trace loss
110A.5 Channel insertion loss <\/td>\n<\/tr>\n
233<\/td>\n110A.6 Channel return loss
110A.7 Channel Operating Margin (COM) <\/td>\n<\/tr>\n
234<\/td>\nAnnex 110B (normative) Test fixtures for 25GBASE-CR, 25GBASE-CR-S, and 25GAUI C2M
110B.1 Test fixtures
110B.1.1 SFP28 TP2 or TP3 test fixture
110B.1.2 SFP28 Cable assembly test fixture <\/td>\n<\/tr>\n
235<\/td>\n110B.1.3 SFP28 Mated test fixtures
110B.1.3.1 Mated test fixtures differential insertion loss
110B.1.3.2 Mated test fixtures differential return loss
110B.1.3.3 Mated test fixtures common-mode conversion insertion loss
110B.1.3.4 Mated test fixtures common-mode return loss
110B.1.3.5 Mated test fixtures common-mode to differential mode return loss
110B.1.3.7 Mated test fixtures integrated near-end crosstalk noise <\/td>\n<\/tr>\n
237<\/td>\n110B.2 Protocol implementation conformance statement (PICS) proforma for Annex 110B, Test fixtures for 25GBASE-CR, 25GBASE-CR-S, and 25GAUI C2M
110B.2.1 Introduction
110B.2.2 Identification
110B.2.2.1 Implementation identification
110B.2.2.2 Protocol summary <\/td>\n<\/tr>\n
238<\/td>\n110B.2.3 Major capabilities\/options
110B.2.4 PICS proforma tables for test fixtures for 25GBASE-CR, 25GBASE-CR-S, and 25GAUI C2M <\/td>\n<\/tr>\n
239<\/td>\nAnnex 110C (informative) Host and cable assembly form factors for 25GBASE-CR and 25GBASE-CR-S PHYs
110C.1 Overview <\/td>\n<\/tr>\n
240<\/td>\n110C.2 Host form factors
110C.2.1 SFP28 host form factor
110C.2.2 QSFP28 host form factor <\/td>\n<\/tr>\n
241<\/td>\n110C.3 Cable assembly form factors
110C.3.1 SFP28 to SFP28 cable assembly form factor <\/td>\n<\/tr>\n
242<\/td>\n110C.3.2 QSFP28 to QSFP28 cable assembly form factor <\/td>\n<\/tr>\n
243<\/td>\n110C.3.3 QSFP28 to 4\u00d7SFP28 cable assembly form factor <\/td>\n<\/tr>\n
244<\/td>\nBack cover <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for Ethernet — Amendment 2: Media Access Control Parameters, Physical Layers, and Management Parameters for 25 Gb\/s Operation Amendment 2: Media Access Control Parameters,
\nPhysical Layers, and Management Parameters for 25 Gb\/s Operation<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2016<\/td>\n244<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":194738,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-194734","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/194734","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/194738"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=194734"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=194734"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=194734"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}