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IEEE 1801 2018:2019 Edition

IEEE 1801 2018:2019 Edition

$183.08

IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems

Published By Publication Date Number of Pages
IEEE 2019 548
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Revision Standard – Active. A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power management architecture, and for driving implementation of that power-management architecture. The method supports incremental refinement of power intent specifications required for IP-based design flows.(The PDF of this standard is available to you at no cost thru the IEEE GET program https://ieeexplore.ieee.org/browse/standards/get-program/page)

PDF Catalog

PDF Pages PDF Title
1 IEEE Std 1801™-2018 Front cover
2 Title page
4 Important Notices and Disclaimers Concerning IEEE Standards Documents
7 Participants
8 Introduction
10 Contents
14 1. Overview
1.1 Scope
1.2 Purpose
1.3 Key characteristics of the Unified Power Format
16 1.4 Contents of this standard
17 2. Normative references
3. Definitions, acronyms, and abbreviations
3.1 Definitions
23 3.2 Acronyms and abbreviations
24 4. Concepts
4.1 Introduction
25 4.2 Design structure
4.3 Design representation
29 4.4 Power architecture
32 4.5 Power distribution
40 4.6 Power management
45 4.7 Supply states and power states
52 4.8 Simstates
53 4.9 Power intent specification
59 5. Language basics
5.1 UPF is Tcl
60 5.2 Conventions used
62 5.3 Lexical elements
66 5.4 Boolean expressions
68 5.5 Object declaration
5.6 Attributes of objects
73 5.7 Precedence
76 5.8 Generic UPF command semantics
77 5.9 effective_element_list semantics
80 5.10 Command refinement
81 5.11 Error handling
5.12 Units
5.13 SystemC language basic
82 6. Power intent commands
6.1 Introduction
6.2 Categories
83 6.3 add_parameter
84 6.4 add_port_state (legacy)
85 6.5 add_power_state
92 6.6 add_pst_state (legacy)
93 6.7 add_state_transition
95 6.8 add_supply_state
96 6.9 apply_power_model
98 6.10 associate_supply_set
100 6.11 begin_power_model (legacy)
101 6.12 bind_checker
103 6.13 connect_logic_net
105 6.14 connect_supply_net
107 6.15 connect_supply_set
108 6.16 create_composite_domain
110 6.17 create_hdl2upf_vct
111 6.18 create_logic_net
112 6.19 create_logic_port
113 6.20 create_power_domain
120 6.21 create_power_state_group
122 6.22 create_power_switch
129 6.23 create_pst (legacy)
130 6.24 create_supply_net
134 6.25 create_supply_port
135 6.26 create_supply_set
137 6.27 create_upf2hdl_vct
138 6.28 define_power_model
140 6.29 describe_state_transition (deprecated)
6.30 end_power_model (legacy)
141 6.31 find_objects
145 6.32 load_simstate_behavior
146 6.33 load_upf
147 6.34 load_upf_protected (deprecated)
6.35 map_power_switch
148 6.36 map_repeater_cell
149 6.37 map_retention_cell
153 6.38 name_format
154 6.39 save_upf
155 6.40 set_correlated
156 6.41 set_design_attributes
157 6.42 set_design_top
158 6.43 set_domain_supply_net (legacy)
159 6.44 set_equivalent
161 6.45 set_isolation
168 6.46 set_level_shifter
174 6.47 set_partial_on_translation
176 6.48 set_port_attributes
182 6.49 set_repeater
186 6.50 set_retention
190 6.51 set_retention_elements
191 6.52 set_scope
192 6.53 set_simstate_behavior
195 6.54 set_variation
196 6.55 sim_assertion_control
198 6.56 sim_corruption_control
201 6.57 sim_replay_control
203 6.58 upf_version
204 6.59 use_interface_cell
206 7. Power-management cell definition commands
7.1 Introduction
207 7.2 define_always_on_cell
208 7.3 define_diode_clamp
209 7.4 define_isolation_cell
212 7.5 define_level_shifter_cell
217 7.6 define_power_switch_cell
219 7.7 define_retention_cell
221 8. UPF processing
8.1 Overview
222 8.2 Data requirements
8.3 Processing phases
226 8.4 Error checking
9. Simulation semantics
9.1 Supply network creation
228 9.2 Supply network simulation
229 9.3 Power state simulation
232 9.4 Power state transition detection
233 9.5 Simstate simulation
235 9.6 Transitioning from one simstate state to another
236 9.7 Simulation of retention
242 9.8 Simulation of isolation
243 9.9 Simulation of level-shifting
9.10 Simulation of repeaters
10. UPF information model
10.1 Overview
244 10.2 Components of UPF information model
245 10.3 Identifiers in information model (IDs)
248 10.4 Classification of objects
254 10.5 Example of design hierarchy
255 10.6 Object definitions
314 11. Information model application programmable interface (API)
11.1 Tcl interface
324 11.2 HDL interface
388 Annex A (informative) Bibliography
389 Annex B (normative) Value conversion tables
B.1 Overview
B.2 VHDL_SL2UPF
B.3 UPF2VHDL_SL
B.4 VHDL_SL2UPF_GNDZERO
390 B.5 UPF_GNDZERO2VHDL_SL
B.6 SV_LOGIC2UPF
B.7 UPF2SV_LOGIC
B.8 SV_LOGIC2UPF_GNDZERO
B.9 UPF_GNDZERO2SV_LOGIC
391 B.10 VHDL_TIED_HI
B.11 SV_TIED_HI
B.12 VHDL_TIED_LO
B.13 SV_TIED_LO
392 Annex C (informative) UPF query examples
C.1 Overview
C.2 Utility procs
393 C.3 High-level procs
395 C.4 Superseded UPF queries
397 Annex D (informative) Replacing deprecated and legacy commands and options
D.1 Overview
D.2 Deprecated and legacy constructs
399 D.3 Recommendations for replacing deprecated and legacy constructs
402 Annex E (informative) Low-power design methodology
E.1 Overview
E.2 Simple System on Chip (SoC) example design
405 E.3 Design, verification, and implementation flow
408 E.4 Power intent of the example design
429 Annex F (informative) Power-management cell definitions in UPF and Liberty
F.1 Introduction
F.2 define_always_on_cell
431 F.3 define_diode_clamp
432 F.4 define_isolation_cell
435 F.5 define_level_shifter_cell
437 F.6 define_power_switch_cell
439 F.7 define_retention_cell
443 Annex G (informative) Power-management cell modeling examples
G.1 Overview
G.2 Modeling always-on cells
449 G.3 Modeling cells with internal diodes
451 G.4 Modeling isolation cells
468 G.5 Modeling level-shifters
485 G.6 Modeling power-switch cells
495 G.7 Modeling state retention cells
507 Annex H (informative) IP power modeling for system-level design
H.1 Introduction
H.2 Overview of system-level IP power models
508 H.3 Content of system-level IP power models
509 H.4 Power calculation using power functions
511 H.5 Power model structure
512 H.6 Power model instantiation—example approach
514 Annex I (normative) Switching Activity Interchange Format
515 I.1 Syntactic conventions
516 I.2 Lexical conventions
519 I.3 Backward SAIF file
535 I.4 Library forward SAIF file
543 I.5 RTL forward SAIF file
548 Back cover

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