IEEE 1394b-2002
$98.04
Standard for High Performance Serial Bus (High Speed Supplement)]
Published By | Publication Date | Number of Pages |
IEEE | 2002 |
Amendment Standard – Superseded. Supplemental information for a high-speed serial bus that integrates well with most IEEE standard 32-bit and 64-bit parallel buses is specified. It is intended to extend the usefulness of a low-cost interconnect between external peripherals. This standard follows the IEEE Std 1212 ™-2001 Command and Status Register (CSR) architecture.
PDF Catalog
PDF Pages | PDF Title |
---|---|
1 | Cover page |
3 | Title page |
5 | Introduction |
7 | Participants |
9 | CONTENTS |
13 | 0.�� Overview 0.1�� Scope |
14 | 0.2�� Purpose 0.3�� Document organization |
15 | 1.�� Overview 1.2�� References |
16 | 1.5�� Service model |
17 | 1.6�� Document notation 1.6.1�� Mechanical notation 1.6.2�� Signal naming |
18 | 1.6.3�� Size notation 1.6.4�� Numerical values |
19 | 1.6.5�� Packet formats 1.6.6�� Register formats 1.6.7�� C code notation |
21 | 1.6.8�� State machine notation 1.6.9�� CSR, ROM, and field notation |
22 | 1.6.10�� Register specification format |
23 | 1.6.11�� Reserved registers and fields |
24 | 1.6.12�� Operation description priorities |
25 | 2.�� Definitions and abbreviations 2.1�� Conformance 2.2�� Technical glossary |
33 | 2.3�� Acronyms and abbreviations |
35 | 3.�� Summary description 3.10�� New features of IEEE Std 1394b-2002 3.10.1�� The relationship to IEEE Std 1394a-2000 3.10.2�� Faster and further |
36 | 3.10.3�� Nomenclature 3.10.4�� Media—common properties |
38 | 3.10.5�� Arbitration improvements |
44 | 3.10.6�� PHY-link interface |
45 | 3.10.7�� Miscellaneous features |
47 | 4.�� Cable PHY specification 4.2.1B�� Copper PMD cable media attachment |
89 | 9.�� Short-haul copper PMD electrical specification |
90 | 9.1�� Interfaces 9.2�� Transmitter electrical specifications |
93 | 9.3�� Receiver electrical specifications |
94 | 9.4�� Electrical measurements 9.4.1�� Transmit rise and fall time 9.4.2�� Transmit skew measurement |
95 | 9.4.3�� Transmit eye (normalized and absolute) 9.5�� DC biasing 9.5.1�� Beta-mode receiver bias requirements 9.6�� Toning and signal detect |
96 | 9.6.1�� Connection tone 9.6.2�� PMD signal detect function |
98 | 9.7�� Jitter 9.7.1�� Jitter specifications |
101 | 10.�� Glass optical fiber physical medium dependent specification 10.1�� PMD block diagram |
102 | 10.2�� PMD to MDI optical specifications |
103 | 10.3�� Transmitter optical specifications 10.4�� Receiver optical specifications |
104 | 10.5�� Worst-case connection optical power budget and penalties (informative) 10.6�� Optical jitter specifications |
106 | 10.7�� Optical measurement requirements 10.7.1�� Center wavelength and spectral width measurements 10.7.2�� Optical power measurements 10.7.3�� Extinction ratio measurements |
107 | 10.7.4�� Relative intensity noise (RIN) 10.7.5�� Transmitter optical waveform (transmit eye) |
108 | 10.7.6�� Transmit rise and fall characteristics 10.7.7�� Receiver sensitivity measurements 10.7.8�� Jitter measurements 10.8�� CPR measurement 10.9�� Optical connection cabling model |
109 | 10.9.1�� Characteristics of the fiber optic medium 10.9.2�� Optical fiber and cable 10.9.3�� Multimode connector insertion loss 10.9.4�� Optical connection return loss 10.10�� Optical connection |
110 | 10.11�� Fiber launch conditions: OLF |
111 | 11.�� PMD specification of fiber media with PN connector 11.1�� Scope |
112 | 11.2�� PMD block diagram 11.3�� Cables |
113 | 11.4�� Connector 11.5�� Connector and cable assembly performance criteria |
114 | 11.6�� Optical fiber interface |
115 | 11.7�� Optical jitter specifications |
116 | 11.8�� Permitted number of segments (informative) |
119 | 12.�� CAT-5 UTP PMD specification 12.1�� Overview |
120 | 12.2�� PMD block diagram 12.3�� Operation of CAT-5 connections 12.4�� Media specification |
121 | 12.4.1�� 100�W UTP connection segment specification 12.4.2�� 100�W UTP cable specification 12.4.3�� Connection hardware 12.4.4�� Media interface connector |
122 | 12.4.5�� Autocrossover 12.5�� PMD electrical specifications 12.5.1�� Galvanic isolation 12.5.2�� Transmitter specifications |
124 | 12.5.3�� Receiver specifications |
126 | 12.6�� PMD implementation (informative) |
127 | 13.�� Beta-mode port specification 13.1�� Overview |
128 | 13.2�� Port functions 13.2.1�� Overview |
129 | 13.2.2�� Naming conventions |
130 | 13.2.3�� Control mapping 13.2.4�� Request types |
132 | 13.2.5�� Scrambling |
136 | 13.2.6�� Coding |
144 | 13.2.7�� Character transmission 13.2.8�� Decoding |
145 | 13.2.9�� Receiver running disparity 13.2.10�� Descrambling 13.3�� Beta-mode port operation 13.3.1�� Transmit operations |
149 | 13.3.2�� Receive operations |
152 | 13.4�� Beta port state machines |
153 | 13.4.1�� Port transmit state machine |
154 | 13.4.2�� Port receive state machine |
157 | 14.�� Connection management 14.1�� Overview |
158 | 14.2�� Port characteristics 14.2.1�� Requirements 14.2.2�� Properties |
159 | 14.3�� Functions, variables, and constants |
161 | 14.4�� Port controller 14.5�� Port connection manager state machine |
166 | 14.6�� Standby 14.6.1�� Nephew node characteristics 14.6.2�� Uncle node characteristics |
167 | 14.7�� Loop prevention |
168 | 14.7.1�� Test port 14.7.2�� Loop test data (LTD) |
169 | 14.7.3�� HR 14.7.4�� Maximum occupancy timer 14.7.5�� Loop-test symbol (LTS) |
170 | 14.7.6�� Loop-test packet (LTP) 14.7.7�� Test port selection 14.7.8�� Loop test |
171 | 14.7.9�� Completing the attach 14.7.10�� Received ATTACH_REQUEST or bus reset |
172 | 14.7.11�� Loop Disabled state 14.7.12�� Connections to Legacy nodes 14.7.13�� Loop detection during bus initialization 14.7.14�� Minimal LTP support 14.7.15�� Isolated node behavior |
173 | 14.8�� Connection management 14.8.1�� Connection detection 14.8.2�� Connection detection and mode determination algorithm |
174 | 14.8.3�� Beta-mode speed negotiation |
176 | 14.8.4�� Disabled ports |
177 | 15.�� PHY register map 15.1�� PHY register map for the cable environment |
180 | 15.1.1�� Port Status page |
183 | 15.1.2�� Vendor Identification page |
184 | 15.2�� Integrated link and PHY |
185 | 16.�� Data routing, arbitration, and control 16.1�� Overview |
186 | 16.2�� PHY services 16.2.1�� Cable PHY bus management services for the management layer |
188 | 16.2.2�� PHY arbitration services for the link layer |
191 | 16.2.3�� PHY data services for the link layer |
192 | 16.2.4�� PHY-link interface block |
193 | 16.2.5�� PMD services for the PHY |
196 | 16.3�� PHY facilities 16.3.1�� Packet formats |
200 | 16.3.2�� Packet forwarding |
201 | 16.3.3�� Cable PHY packets |
206 | 16.3.4�� Cable interface timing constants |
208 | 16.4�� Cable PHY operation 16.4.1�� C code functions and variables |
210 | 16.4.2�� Beta-mode arbitration |
212 | 16.4.3�� Hybrid bus operation |
216 | 16.4.4�� Isochronous intervals |
219 | 16.4.5�� Bus reset state machine |
220 | 16.4.6�� Tree identification state machine |
222 | 16.4.7�� Self-identification state machine |
225 | 16.4.8�� Arbitration state machine |
229 | 17.�� B PHY- link interface (parallel) 17.1�� B PHY-link interface characteristics |
230 | 17.2�� PHY-link interface signals 17.2.1�� Interface signal descriptions |
232 | 17.3�� Interface initialization, reset, and disable 17.3.1�� LPS signal characteristics |
233 | 17.3.2�� Interface reset |
234 | 17.3.3�� Interface disable 17.3.4�� Restoration and initialization |
236 | 17.4�� Link-on and interrupt indications 17.4.1�� LinkOn signal characteristics |
237 | 17.5�� Link requests and notifications 17.5.1�� Link request characteristics |
240 | 17.5.2�� Link notifications |
241 | 17.5.3�� Link request and notification format |
243 | 17.6�� Interface data transfers 17.6.1�� Interface phases 17.6.2�� Packet reception |
245 | 17.6.3�� Packet transmission |
250 | 17.7�� Format of received and transmitted data 17.7.1�� S100 data |
251 | 17.7.2�� S200 data 17.7.3�� S400 data 17.7.4�� S800 data |
252 | 17.8�� Status transfers and notifications from the PHY 17.8.1�� Bus Status Transfers |
253 | 17.8.2�� PHY Status Transfers |
255 | 17.9�� Delays affecting interoperability of PHYs and links |
256 | 17.10�� Legacy link support |
257 | 17.11�� Electrical characteristics 17.11.1�� DC signal levels and waveforms |
258 | 17.11.2�� AC timing |
260 | 17.11.3�� Isolation barrier (informative) |
262 | 17.11.4�� Alternative isolation barrier (informative) |
265 | 18.�� PIL-FOP serial interface 18.1�� Operating model |
266 | 18.2�� PIL-FOP connection management 18.2.1�� Power-on 18.2.2�� PIL-FOP negotiation |
267 | 18.2.3�� PIL-FOP restore 18.2.4�� Port restore 18.2.5�� Loss of synchronization 18.2.6�� Loss of power 18.2.7�� LPS |
268 | 18.2.8�� Serial Bus reset 18.3�� Serial Bus configuration request types not carried over the PIL-FOP interface 18.4�� P2P packet protocol |
271 | 19.�� C code 19.1�� Common declarations and functions |
285 | 19.2�� Connection management routines 19.2.1�� Node-level connection monitor |
293 | 19.2.2�� Port connection manager actions and conditions |
307 | 19.3�� Port state machine actions 19.3.1�� DS port |
313 | 19.3.2�� Beta port |
326 | 19.4�� Border arbitration actions and conditions 19.4.1�� Border arbitration functions |
345 | 19.4.2�� Request processing |
353 | 19.4.3�� Bus reset |
356 | 19.4.4�� Tree identification |
357 | 19.4.5�� Self-identification |
361 | 19.5�� Border arbitration |
373 | Annex K—Serial Bus cable test procedures |
377 | Annex O—Jitter measurements |
379 | Annex P—Connection status change |
381 | Annex Q—Bibliography |