EIA 567-A-1995

$33.15

VHDL Hardware Component Modeling and Interface Standard

Published By	Publication Date	Number of Pages
ECIA	1995	48

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Description

This standard defines concepts, terminology, and information
required for constructing a VHDL component model to be used in a
hierarchical design and simulated interoperably with other models
conforming to this standard.

Purpose

In order to specify and simulate a complex hardware system
consisting of multiple components, it is necessary to define common
modeling interfaces. conventions, and simulation modes. Commonality
assures that any new components developed for the hardware system
can be simulated together. Commonalty also assures that new
components will simulate with component models obtained from
standard libraries or reused from previous designs. The purpose of
this specification is to provide guidelines for the production of
VHDL models for hardware descriptions that:

• conform to a common signal interface convention

• possess common simulation capabilities

• are reusable as library elements of other designs

• support multiple source procurement

• support technology independent reprocurement

It is not the purpose of this specification to create models
that promote a particular hardware design methodology.

Additional information