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BS IEC 61691-6:2021

BS IEC 61691-6:2021

$215.11

Behavioural languages – VHDL Analog and Mixed-Signal Extensions

Published By Publication Date Number of Pages
BSI 2021 676
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This standard defines the IEEE 1076.1ā„¢ language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. Informally called VHDL-AMS (VHSIC Hardware Description Language for Analog and Mixed-Signal, where VHSIC stands for Very High Speed Integrated Circuits), the language is built on the IEEE 1076ā„¢ (VHDL) language and extends it to provide capabilities of writing and simulating analog and mixed-signal models.

PDF Catalog

PDF Pages PDF Title
2 undefined
4 Contents
17 Introduction
19 1. Overview
1.1 Scope
1.2 Purpose
1.3 Structure and terminology of this standard
1.3.1 General
20 1.3.2 Syntactic description
21 1.3.3 Semantic description
1.3.4 Front matter, examples, notes, references, and annexes
1.3.5 Incorporation of Property Specification Language
22 2. Normative references
23 3. Design entities and configurations
3.1 General
3.2 Entity declarations
3.2.1 General
24 3.2.2 Entity header
3.2.3 Entity declarative part
26 3.2.4 Entity statement part
3.3 Architecture bodies
3.3.1 General
27 3.3.2 Architecture declarative part
28 3.3.3 Architecture statement part
29 3.4 Configuration declarations
3.4.1 General
30 3.4.2 Block configuration
33 3.4.3 Component configuration
36 4. Subprograms and packages
4.1 General
4.2 Subprogram declarations
4.2.1 General
37 4.2.2 Formal parameters
4.2.2.1 Formal parameter lists
38 4.2.2.2 Constant and variable parameters
39 4.2.2.3 Signal parameters
40 4.2.2.4 File parameters
4.3 Subprogram bodies
43 4.4 Subprogram instantiation declarations
44 4.5 Subprogram overloading
4.5.1 General
45 4.5.2 Operator overloading
4.5.3 Signatures
46 4.6 Resolution functions
47 4.7 Package declarations
49 4.8 Package bodies
50 4.9 Package instantiation declarations
51 4.10 Conformance rules
52 5. Types and natures
5.1 General
53 5.2 Scalar types
5.2.1 General
54 5.2.2 Enumeration types
5.2.2.1 General
55 5.2.2.2 Predefined enumeration types
5.2.3 Integer types
5.2.3.1 General
56 5.2.3.2 Predefined integer types
5.2.4 Physical types
5.2.4.1 General
58 5.2.4.2 Predefined physical types
59 5.2.5 Floating-point types
5.2.5.1 General
60 5.2.5.2 Predefined floating-point types
5.2.6 Predefined operations on scalar types
61 5.3 Composite types
5.3.1 General
62 5.3.2 Array types
5.3.2.1 General
64 5.3.2.2 Index constraints and discrete ranges
67 5.3.2.3 Predefined array types
68 5.3.2.4 Predefined operations on array types
69 5.3.3 Record types
71 5.4 Access types
5.4.1 General
5.4.2 Incomplete type declarations
72 5.4.3 Allocation and deallocation of objects
73 5.5 File types
5.5.1 General
5.5.2 File operations
76 5.6 Protected types
5.6.1 Protected type definitions
5.6.2 Protected type declarations
77 5.6.3 Protected type bodies
79 5.7 String representations
80 5.8 Natures
5.8.1 General
5.8.2 Scalar natures
81 5.8.3 Composite natures
5.8.3.1 General
5.8.3.2 Array natures
82 5.8.3.3 Record natures
85 6. Declarations
6.1 General
86 6.2 Type declarations
6.3 Subtype declarations
88 6.4 Objects
6.4.1 General
89 6.4.2 Object declarations
6.4.2.1 General
90 6.4.2.2 Constant declarations
6.4.2.3 Signal declarations
92 6.4.2.4 Variable declarations
94 6.4.2.5 File declarations
95 6.4.2.6 Terminal declarations
96 6.4.2.7 Quantity declarations
99 6.5 Interface declarations
6.5.1 General
6.5.2 Interface object declarations
102 6.5.3 Interface type and interface nature declarations
6.5.3.1 Interface type declarations
6.5.3.2 Interface nature declarations
103 6.5.4 Interface subprogram declarations
104 6.5.5 Interface package declarations
6.5.6 Interface lists
6.5.6.1 General
105 6.5.6.2 Generic clauses
106 6.5.6.3 Port clauses
108 6.5.7 Association lists
6.5.7.1 General
111 6.5.7.2 Generic map aspects
115 6.5.7.3 Port map aspects
117 6.6 Alias declarations
6.6.1 General
6.6.2 Object aliases
118 6.6.3 Nonobject aliases
120 6.7 Attribute declarations
121 6.8 Component declarations
6.9 Group template declarations
6.10 Group declarations
122 6.11 Nature and subnature declarations
123 6.12 PSL clock declarations
124 7. Specifications
7.1 General
7.2 Attribute specification
127 7.3 Configuration specification
7.3.1 General
128 7.3.2 Binding indication
7.3.2.1 General
130 7.3.2.2 Entity aspect
131 7.3.3 Default binding indication
132 7.3.4 Verification unit binding indication
133 7.4 Disconnection specification
135 7.5 Step limit specification
138 8. Names
8.1 General
139 8.2 Simple names
140 8.3 Selected names
142 8.4 Indexed names
143 8.5 Slice names
8.6 Attribute names
144 8.7 External names
148 9. Expressions
9.1 General
149 9.2 Operators
9.2.1 General
150 9.2.2 Logical operators
151 9.2.3 Relational operators
154 9.2.4 Shift operators
156 9.2.5 Adding operators
158 9.2.6 Sign operators
9.2.7 Multiplying operators
160 9.2.8 Miscellaneous operators
161 9.2.9 Condition operator
162 9.3 Operands
9.3.1 General
9.3.2 Literals
163 9.3.3 Aggregates
9.3.3.1 General
164 9.3.3.2 Record aggregates
9.3.3.3 Array aggregates
167 9.3.4 Function calls
9.3.5 Qualified expressions
168 9.3.6 Type conversions
169 9.3.7 Allocators
170 9.4 Static expressions
9.4.1 General
9.4.2 Locally static primaries
172 9.4.3 Globally static primaries
174 9.5 Universal expressions
9.6 Linear forms
177 10 Sequential statements
10.1 General
10.2 Wait statement
179 10.3 Assertion statement
180 10.4 Report statement
181 10.5 Signal assignment statement
10.5.1 General
10.5.2 Simple signal assignments
10.5.2.1 General
184 10.5.2.2 Executing a simple assignment statement
187 10.5.3 Conditional signal assignments
190 10.5.4 Selected signal assignments
192 10.6 Variable assignment statement
10.6.1 General
10.6.2 Simple variable assignments
10.6.2.1 General
193 10.6.2.2 Composite variable assignments
10.6.3 Conditional variable assignments
195 10.6.4 Selected variable assignments
196 10.7 Procedure call statement
10.8 If statement
197 10.9 Case statement
199 10.10 Loop statement
10.11 Next statement
200 10.12 Exit statement
10.13 Return statement
201 10.14 Null statement
10.15 Break statement
202 11. Architecture statements
11.1 General
203 11.2 Block statement
204 11.3 Process statement
206 11.4 Concurrent procedure call statements
207 11.5 Concurrent assertion statements
208 11.6 Concurrent signal assignment statements
210 11.7 Component instantiation statements
11.7.1 General
211 11.7.2 Instantiation of a component
213 11.7.3 Instantiation of a design entity
216 11.8 Generate statements
218 11.9 Concurrent break statement
219 11.10 Simple simultaneous statement
220 11.11 Simultaneous if statement
11.12 Simultaneous case statement
221 11.13 Simultaneous procedural statement
224 11.14 Simultaneous null statement
225 12. Scope and visibility
12.1 Declarative region
12.2 Scope of declarations
227 12.3 Visibility
231 12.4 Use clauses
232 12.5 The context of overload resolution
234 13. Design units and their analysis
13.1 Design units
13.2 Design libraries
236 13.3 Context declarations
13.4 Context clauses
237 13.5 Order of analysis
238 14. Elaboration and execution
14.1 General
14.2 Elaboration of a design hierarchy
242 14.3 Elaboration of a block, package, or subprogram header
14.3.1 General
14.3.2 Generic clause
14.3.3 Generic map aspect
14.3.3.1 General
14.3.3.2 Association elements for generic constants
243 14.3.3.3 Association elements for generic types and natures
14.3.3.4 Association elements for generic subprograms
14.3.3.5 Association elements for generic packages
14.3.4 Port clause
14.3.5 Port map aspect
245 14.4 Elaboration of a declarative part
14.4.1 General
246 14.4.2 Elaboration of a declaration
14.4.2.1 General
14.4.2.2 Subprogram declarations, bodies, and instantiations
14.4.2.3 Type declarations
247 14.4.2.4 Subtype declarations
14.4.2.5 Object declarations
248 14.4.2.6 Alias declarations
14.4.2.7 Attribute declarations
249 14.4.2.8 Component declarations
14.4.2.9 Packages
14.4.2.10 Nature and subnature declarations
14.4.3 Elaboration of a specification
14.4.3.1 General
14.4.3.2 Attribute specifications
250 14.4.3.3 Configuration specifications
14.4.3.4 Disconnection specifications
14.4.3.5 Step limit specifications
14.5 Elaboration of a statement part
14.5.1 General
251 14.5.2 Block statements
14.5.3 Generate statements
253 14.5.4 Component instantiation statements
14.5.5 Other concurrent statements
254 14.5.6 Simultaneous statements
14.6 Dynamic elaboration
255 14.7 Execution of a model
14.7.1 General
14.7.2 Drivers
256 14.7.3 Propagation of signal values
14.7.3.1 General
257 14.7.3.2 Driving values
258 14.7.3.3 Effective values
259 14.7.3.4 Signal update
260 14.7.4 Updating implicit signals
262 14.7.5 Model execution
14.7.5.1 General
14.7.5.2 Initialization
263 14.7.5.3 Simulation cycle
265 14.7.6 Augmentation sets
14.7.6.1 General
14.7.6.2 Quiescent state augmentation set
266 14.7.6.3 Time domain augmentation set
14.7.6.4 Discontinuity augmentation set
267 14.7.6.5 Frequency domain augmentation set
268 14.7.6.6 Noise augmentation set
14.7.7 Analog solver
14.7.7.1 General
270 14.7.7.2 Application of the break set
14.8 Time and the analog solver
271 14.9 Frequency and noise calculation
273 15. Lexical elements
15.1 General
15.2 Character set
275 15.3 Lexical elements, separators, and delimiters
277 15.4 Identifiers
15.4.1 General
15.4.2 Basic identifiers
15.4.3 Extended identifiers
278 15.5 Abstract literals
15.5.1 General
15.5.2 Decimal literals
15.5.3 Based literals
279 15.6 Character literals
15.7 String literals
280 15.8 Bit string literals
282 15.9 Comments
283 15.10 Reserved words
285 15.11 Tool directives
286 16. Predefined language environment
16.1 General
16.2 Predefined attributes
16.2.1 General
16.2.2 Predefined attributes of types and objects
289 16.2.3 Predefined attributes of arrays
291 16.2.4 Predefined attributes of signals
294 16.2.5 Predefined attributes of named entities
300 16.2.6 Predefined analog and mixed-signal attributes
308 16.3 Package STANDARD
323 16.4 Package TEXTIO
329 16.5 Standard environment package
330 16.6 Standard mathematical packages
331 16.7 Standard multivalue logic package
16.8 Standard synthesis packages
16.8.1 Overview
16.8.1.1 Scope
332 16.8.1.2 Terminology
16.8.2 Interpretation of the standard logic types
16.8.2.1 General
16.8.2.2 The STD_LOGIC_1164 values
333 16.8.2.3 Static constant values
16.8.2.4 Interpretation of logic values
335 16.8.3 The STD_MATCH function and predefined matching relational operators
16.8.4 Signal edge detection
16.8.5 Packages for arithmetic using bit and standard logic values
16.8.5.1 General
336 16.8.5.2 Allowable modifications
337 16.8.5.3 Compatibility with previous editions of IEEE Std 1076
16.8.5.4 The package texts
16.9 Standard synthesis context declarations
338 16.10 Fixed-point package
16.11 Floating-point package
339 16.12 Standard packages for multiple energy domain support
16.12.1 Scope
16.12.2 Organization of the packages
16.12.3 The package texts
340 17. VHDL Procedural Interface overview
17.1 General
17.2 Organization of the interface
17.2.1 General
341 17.2.2 VHPI naming conventions
17.3 Capability sets
343 17.4 Handles
17.4.1 General
17.4.2 Handle creation
17.4.3 Handle release
344 17.4.4 Handle comparison
17.4.5 Validity of handles
345 18. VHPI access functions
18.1 General
18.2 Information access functions
18.2.1 General
18.2.2 One-to-one association traversal
346 18.2.3 One-to-many association traversal
347 18.3 Property access functions
18.3.1 General
18.3.2 Integer and Boolean property access function
18.3.3 String property access function
348 18.3.4 Real property access function
18.3.5 Physical property access function
18.4 Access by name function
349 19. VHPI information model
19.1 General
19.2 Formal notation
19.2.1 General
19.2.2 Machine-readable information model
350 19.3 Class inheritance hierarchy
351 19.4 Name properties
19.4.1 General
19.4.2 Implicit labels of statements
19.4.2.1 General
19.4.2.2 Implicit labels of loop statements
352 19.4.2.3 Implicit labels of concurrent statements
19.4.3 The Name and CaseName properties
357 19.4.4 The SignatureName property
19.4.5 The UnitName property
19.4.6 The DefName and DefCaseName properties
361 19.4.7 The FullName and FullCaseName properties
364 19.4.8 The PathName and InstanceName properties
19.5 The stdUninstantiated package
367 19.6 The stdHierarchy package
374 19.7 The stdTypes package
376 19.8 The stdExpr package
379 19.9 The stdSpec package
381 19.10 The stdSubprograms package
383 19.11 The stdStmts package
389 19.12 The stdConnectivity package
19.12.1 Class diagrams
392 19.12.2 Contributors, loads, and simulated nets
19.12.2.1 General
393 19.12.2.2 Local contributors
394 19.12.2.3 Local loads
19.12.2.4 Simulated nets
19.13 The stdCallbacks package
395 19.14 The stdEngine package
19.15 The stdForeign package
19.16 The stdMeta package
397 19.17 The stdTool package
398 19.18 Application contexts
399 20. VHPI tool execution
20.1 General
20.2 Registration phase
20.2.1 General
400 20.2.2 Registration using a tabular registry
402 20.2.3 Registration using registration functions
403 20.2.4 Foreign attribute for foreign models
20.2.4.1 General
20.2.4.2 Standard indirect binding
404 20.2.4.3 Standard direct binding
405 20.3 Analysis phase
20.4 Elaboration phase
20.4.1 General
406 20.4.2 Dynamic elaboration
407 20.5 Initialization phase
20.6 Simulation phase
20.7 Save phase
408 20.8 Restart phase
20.9 Reset phase
409 20.10 Termination phase
410 21. VHPI callbacks
21.1 General
21.2 Callback functions
21.2.1 General
21.2.2 Registering callbacks
411 21.2.3 Enabling and disabling callbacks
21.2.4 Removing callbacks
21.2.5 Callback information
21.2.6 Execution of callbacks
412 21.3 Callback reasons
21.3.1 General
21.3.2 Object callbacks
21.3.2.1 General
413 21.3.2.2 vhpiCbValueChange
21.3.2.3 vhpiCbForce
414 21.3.2.4 vhpiCbRelease
21.3.2.5 vhpiCbTransaction
21.3.3 Foreign model callbacks
21.3.3.1 General
21.3.3.2 vhpiCbTimeOut and vhpiCbRepTimeOut
415 21.3.3.3 vhpiCbSensitivity
416 21.3.4 Statement callbacks
21.3.4.1 General
21.3.4.2 vhpiCbStmt
417 21.3.4.3 vhpiCbResume
21.3.4.4 vhpiCbSuspend
21.3.4.5 vhpiCbStartOfSubpCall
418 21.3.4.6 vhpiCbEndOfSubpCall
21.3.5 Time callbacks
21.3.5.1 General
21.3.5.2 vhpiCbAfterDelay and vhpiCbRepAfterDelay
419 21.3.6 Simulation phase callbacks
21.3.6.1 General
21.3.6.2 vhpiCbNextTimeStep and vhpiCbRepNextTimeStep
21.3.6.3 vhpiCbStartOfNextCycle and vhpiCbRepStartOfNextCycle
21.3.6.4 vhpiCbStartOfProcesses and vhpiCbRepStartOfProcesses
21.3.6.5 vhpiCbEndOfProcesses and vhpiCbRepEndOfProcesses
21.3.6.6 vhpiCbLastKnownDeltaCycle and vhpiCbRepLastKnownDeltaCycle
21.3.6.7 vhpiCbStartOfPostponed and vhpiCbRepStartOfPostponed
21.3.6.8 vhpiCbEndOfTimeStep and vhpiCbRepEndOfTimeStep
420 21.3.7 Action callbacks
21.3.7.1 General
21.3.7.2 vhpiCbStartOfTool and vhpiCbEndOfTool
21.3.7.3 vhpiCbStartOfAnalysis and vhpiCbEndOfAnalysis
21.3.7.4 vhpiCbStartOfElaboration and vhpiCbEndOfElaboration
21.3.7.5 vhpiCbStartOfInitialization and vhpiCbEndOfInitialization
421 21.3.7.6 vhpiCbStartOfSimulation and vhpiCbEndOfSimulation
21.3.7.7 vhpiCbQuiescense
21.3.7.8 vhpiCbEnterInteractive
21.3.7.9 vhpiCbExitInteractive
21.3.7.10 vhpiCbSigInterrupt
422 21.3.8 Save, restart, and reset callbacks
21.3.8.1 General
21.3.8.2 vhpiCbStartOfSave and vhpiCbEndOfSave
21.3.8.3 vhpiCbStartOfRestart and vhpiCbEndOfRestart
423 21.3.8.4 vhpiCbStartOfReset and vhpiCbEndOfReset
424 22. VHPI value access and update
22.1 General
22.2 Value structures and types
22.2.1 General
22.2.2 vhpiEnumT and vhpiSmallEnumT
22.2.3 vhpiIntT and vhpiLongIntT
22.2.4 vhpiCharT
22.2.5 vhpiRealT
22.2.6 vhpiPhysT and vhpiSmallPhysT
425 22.2.7 vhpiTimeT
22.2.8 vhpiValueT
427 22.3 Reading object values
428 22.4 Formatting values
430 22.5 Updating object values
22.5.1 General
431 22.5.2 Updating an object of class variable
22.5.3 Updating an object of class signal
433 22.5.4 Updating an object of class driver
434 22.5.5 Updating an object of class funcCall
22.6 Scheduling transactions on drivers
437 23. VHPI function reference
23.1 General
23.2 vhpi_assert
438 23.3 vhpi_check_error
440 23.4 vhpi_compare_handles
441 23.5 vhpi_control
443 23.6 vhpi_create
445 23.7 vhpi_disable_cb
23.8 vhpi_enable_cb
446 23.9 vhpi_format_value
448 23.10 vhpi_get
23.11 vhpi_get_cb_info
449 23.12 vhpi_get_data
451 23.13 vhpi_get_foreignf_info
452 23.14 vhpi_get_next_time
453 23.15 vhpi_get_phys
454 23.16 vhpi_get_real
455 23.17 vhpi_get_str
23.18 vhpi_get_time
456 23.19 vhpi_get_value
457 23.20 vhpi_handle
458 23.21 vhpi_handle_by_index
461 23.22 vhpi_handle_by_name
463 23.23 vhpi_is_printable
23.24 vhpi_iterator
464 23.25 vhpi_printf
465 23.26 vhpi_protected_call
467 23.27 vhpi_put_data
469 23.28 vhpi_put_value
470 23.29 vhpi_register_cb
472 23.30 vhpi_register_foreignf
474 23.31 vhpi_release_handle
23.32 vhpi_remove_cb
475 23.33 vhpi_scan
476 23.34 vhpi_schedule_transaction
479 23.35 vhpi_vprintf
480 24. Standard tool directives
24.1 Protect tool directives
24.1.1 General
482 24.1.2 Protect directives
24.1.2.1 Protect begin directive
24.1.2.2 Protect end directive
24.1.2.3 Protect begin protected directive
24.1.2.4 Protect end protected directive
24.1.2.5 Protect author directive
24.1.2.6 Protect author info directive
483 24.1.2.7 Protect encrypt agent directive
24.1.2.8 Protect encrypt agent info directive
24.1.2.9 Protect key keyowner directive
24.1.2.10 Protect key keyname directive
24.1.2.11 Protect key method directive
24.1.2.12 Protect key block directive
484 24.1.2.13 Protect data keyowner directive
24.1.2.14 Protect data keyname directive
24.1.2.15 Protect data method directive
24.1.2.16 Protect data block directive
24.1.2.17 Protect digest keyowner directive
24.1.2.18 Protect digest keyname directive
24.1.2.19 Protect digest key method directive
485 24.1.2.20 Protect digest method directive
24.1.2.21 Protect digest block directive
24.1.2.22 Protect encoding directive
486 24.1.2.23 Protect viewport directive
487 24.1.2.24 Protect license directives
488 24.1.2.25 Protect comment directive
24.1.3 Encoding, encryption, and digest methods
24.1.3.1 Encoding methods
489 24.1.3.2 Encryption methods
490 24.1.3.3 Digest methods
491 24.1.4 Encryption envelopes
24.1.4.1 General
492 24.1.4.2 Encrypt key specifications
24.1.4.3 Encrypt data specifications
493 24.1.4.4 Encrypt digest specifications
24.1.5 Decryption envelopes
24.1.5.1 General
494 24.1.5.2 Decrypt key blocks
495 24.1.5.3 Decrypt data blocks
24.1.5.4 Decrypt digest blocks
496 24.1.6 Protection requirements for decryption tools
497 Annex A (informative) Description of accompanying files
501 Annex B (informative) VHPI header file
527 Annex C (informative) Syntax summary
555 Annex D (informative) Potentially nonportable constructs
556 Annex E (informative) Changes from IEEE Std 1076.1-2007
559 Annex F (informative) Features under consideration for removal
560 Annex G (informative) Guide to use of standard packages
598 Annex H (informative) Guide to use of protect directives
604 Annex I (informative) Glossary
633 Annex J (informative) Bibliography
636 Index
A
638 B
640 C
642 D
645 E
648 F
650 G
651 H
I
654 J
K
L
655 M
656 N
658 O
659 P
662 Q
R
664 S
669 T
671 U
672 V
675 W
X
Z

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