BS EN IEC 61869-9:2019
$198.66
Instrument transformers – Digital interface for instrument transformers
| Published By | Publication Date | Number of Pages |
| BSI | 2019 | 66 |
IEC 61869-9:2016 is a product family standard applicable to instrument transformers with digital output. The product standard is composed of IEC 61869-1 and IEC 61869-6, in addition to this standard and the relevant product specific standards in the IEC 61869 series (Part 7, Part 8, Part 12, Part 13, Part 14, and Part 15). This standard defines requirements for digital communications of instrument transformer measurements. It is based on the IEC 61850 series, UCA international users group document Implementation guideline for digital interface to instrument transformers using IEC 61850-9-2, and the relevant parts of IEC 60044-8 that are replaced by this standard. It includes additional improvements including the IEC 61588 network based time synchronization. This first edition replaces the corresponding specific requirements previously contained in IEC 60044-8, published in 2002. This International Standard contains specific requirements for electronic low power instrument transformers (LPIT) having a digital output. However, the reader is encouraged to use its most recent edition. This publication contains an attached file in the form of a .xml file. This file is intended to be used as a complement and does not form an integral part of the publication.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 2 | National foreword |
| 7 | CONTENTS |
| 9 | FOREWORD |
| 12 | INTRODUCTION |
| 13 | Figures Figure 901 – General block diagram of an electronic LPIT with digital output |
| 14 | Figure 902 – General illustration of the objects within a merging unit (example) |
| 15 | Figure 903 – Electronic LPIT with digital output (concept example) |
| 16 | Figure 904 – Standalone merging unit |
| 17 | 1 Scope 2 Normative references |
| 18 | 3 Terms and definitions 3.5 Terms and definitions related to other ratings 3.7 Index of abbreviations |
| 19 | 4 Normal and special service conditions 5 Ratings 5.6 Rated accuracy class |
| 20 | 5.901 Performance requirements |
| 21 | 6 Design and construction 6.901 Technological boundaries 6.901.1 Interface point 6.901.2 Digital output interface 6.901.3 Human-machine interface Figure 905 – Duplex LC connector |
| 22 | 6.902 Electrical requirements 6.902.1 Frequency response requirements 6.902.2 Maximum processing delay time requirement Figure 906 – Maximum processing delay time |
| 23 | Tables Table 901 – Maximum processing delay time limits |
| 24 | 6.903 Specification of the communications profile 6.903.1 General 6.903.2 Variants Figure 907 – Output message timestamp point |
| 25 | 6.903.3 Digital output sample rates Table 902 – Standard sample rates |
| 26 | 6.903.4 Logical devices 6.903.5 Logical nodes LPHD 6.903.6 Logical nodes LLN0 6.903.7 Logical nodes TCTR Table 903 – Extensions to the LPHD class |
| 28 | Figure 908 – TCTR naming example Table 904 – AmpSv object attribute values |
| 29 | 6.903.8 Logical nodes TVTR Table 905 – Extensions to the TCTR class |
| 30 | 6.903.9 Quality Table 906 – VolSv object attribute values Table 907 – Extensions to the TVTR class |
| 31 | 6.903.10 Dataset(s) |
| 32 | 6.903.11 Multicast sampled value control block(s) 6.903.12 Configuration of the merging unit |
| 33 | 6.903.13 Rated conformance classes Table 908 – Configuration parameters of the merging unit |
| 34 | Table 909 – Basic conformance statement Table 910 – ACSI models conformance statement |
| 36 | Table 911 – ACSI service conformance statement |
| 38 | Table 912 – PICS for A-Profile support |
| 39 | 6.904 Synchronization 6.904.1 General 6.904.2 Precision time protocol synchronization Table 913 – PICS for T-Profile support |
| 40 | 6.904.3 1PPS synchronization 6.904.4 Sample value message SmpSynch attribute Figure 909 – 1PPS signal waveform at the merging unit clock input |
| 41 | 6.904.5 Holdover mode |
| 42 | 6.904.6 Free-running mode 6.904.7 Time adjustments Figure 910 – Time adjustment example (6 ASDU example) |
| 43 | 7 Tests 7.2 Type tests 7.2.6 Test for accuracy 7.2.901 Digital output conformance tests 7.2.902 Maximum processing delay time test |
| 44 | 7.2.903 Loss of synchronization tests 7.2.904 1PPS test |
| 45 | Annex 9A(informative)Dynamic range considerations |
| 46 | Figure 9A.1 – Nomogram for current |
| 47 | Figure 9A.2 – Nomogram for voltage |
| 48 | Annex 9B(informative)Time synchronization and management example Figure 9B.1 – Sampled value signal processing example showing 2ASDUsper message (F4800S2I4U4 example) |
| 50 | Annex 9C(informative)Example merging unit ICD file |
| 61 | Annex 9D(informative)Test circuits for accuracy measurement Figure 9D.1 – Example test circuit |
| 63 | Figure 9D.2 – Example test circuit |
| 64 | Annex 9E(informative)Electronic nameplate |
| 65 | Bibliography |
